Search - lms in vhdl

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[VHDL-FPGA-Verilog] FPGA_LMS DL : 1: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Update : 2025-02-17 Size : 264kb Publisher : 黄鹤
[Special Effects] 011010 DL : 0: DCT在MATLAB中的实现试过了，可以用，有详细讲解-DCT in the MATLAB tried to achieve that can be used, explained in detail
Update : 2025-02-17 Size : 3kb Publisher : 王芳
[Other] zishiyinglvbodebiyesheji DL : 0: 论文针对数字通信系统中，由于码间串扰(ISI)和信道加性噪声的干扰，导致信号在接收端产生误码，设计了基于LMS算法的自适应均衡器(滤波器)，并通过硬件描述语言VHDL和现场可编程逻辑器件FPGA实现均衡器的硬件实现。是一篇标准的毕业论文,有需要的朋友可以拿来做参考-Thesis for digital communications systems, crosstalk due to inter-symbol (ISI) and additive noise channel interference, leading to signals generated in the receiver error, design algorithm based on LMS adaptive equalizer (filter), and through hardware description languages VHDL and Field Programmable Logic Device FPGA hardware equalizer realize realize. Is a standard thesis, there is a need to make friends can be used as reference
Update : 2025-02-17 Size : 2.24mb Publisher : YZ
[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar DL : 0: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Update : 2025-02-17 Size : 14kb Publisher : Arun
[VHDL-FPGA-Verilog] fir_lms DL : 0: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Update : 2025-02-17 Size : 12kb Publisher : 田文军
[VHDL-FPGA-Verilog] AdaptiveLMSequalizer DL : 0: 通信中的用的LMS均衡算法VHDL实现，代码不长，很容易看懂-Communication with the LMS equalization algorithm to achieve VHDL code is not long, it is easy to understand
Update : 2025-02-17 Size : 3kb Publisher : 王王
[VHDL-FPGA-Verilog] LMS_filter DL : 0: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Update : 2025-02-17 Size : 342kb Publisher : rayax
[VHDL-FPGA-Verilog] ERROR_COUNTING_BLOCK DL : 0: vhdl code for error counting blk in lms algorithm
Update : 2025-02-17 Size : 5kb Publisher : lekshmi
[VHDL-FPGA-Verilog] LMS-vhdl-coad- DL : 0: 基于quartus的LMS 自适应滤波器代码，适合初学者 -The LMS adaptive filter based on quartus code, suitable for beginners
Update : 2025-02-17 Size : 15kb Publisher : jialiangquan
[VHDL-FPGA-Verilog] lms-filter.vhd DL : 0: LMS filter how to write in VHDL form in simple logic
Update : 2025-02-17 Size : 9kb Publisher : suhirdham
[VHDL-FPGA-Verilog] vhdl_lms DL : 0: vhdl 语言实现的lms算法的自适应滤波器两种实现方式包括改进-VHDL language lms algorithm adaptive filter implemented in two ways including improved
Update : 2025-02-17 Size : 45kb Publisher : zhanshen
[Software Engineering] Nouveau-document-texte DL : 0: adaptatif filter lms in vhdl
Update : 2025-02-17 Size : 1kb Publisher : lolo