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[VHDL-FPGA-Verilog] lpc

Description: LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
Platform: | Size: 5120 | Author: 饶进平 | Hits:

[VHDL-FPGA-Verilog] lpc_peri

Description: LPC periph，VHDL and verilog version design， lattice
Platform: | Size: 5120 | Author: Sean Wu | Hits:

[ADO-ODBC] fdfd

Description: 第二章 设计思路 2.1 设计总体框图 有分析可知，本次课程设计可以分成五个木块来实现相应的功能，分别是输入模块，计算模块，扫描模块，输出模块以及显示模块。((Calculator design based on FPGA DE2 development board. language use Verilog. Matrix keyboard input, LCD1602 display. Program includes key scanning module and LCD module and data process module, etc.)alculator\db\calculator.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd calculator\db\calculator.cycloneive_io_sim_cache.45um_ii_1200mv_0c_slow.hsd calculator\db\calculator.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd calculator\db\calculator.db_info calculator\db\calculator.fit.qmsg calculator\db\calculator.hier_info calculator\db\calculator.hif calculator\db\calculator.ipinfo calculator\db\calculator.lpc.html)
Platform: | Size: 1024 | Author: fsfsfsfs | Hits:

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