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[VHDL-FPGA-Verilog] HwLog10

Description: 用verilog写的，基于查表法实现的LOG10运算器，在Altera FPGA中应用。-It is a verilog design of LOG10 calculation unit, which is based on LUT arithmatic. And it is applicated in Altera FPGA.
Platform: | Size: 13312 | Author: vincent | Hits:

[VHDL-FPGA-Verilog] fullsine

Description: This a code for sine wave generation in modelsim. The code is written in verilog. An LUT has to be added to this program to work completely.-This is a code for sine wave generation in modelsim. The code is written in verilog. An LUT has to be added to this program to work completely.
Platform: | Size: 1024 | Author: Jithu | Hits:

[VHDL-FPGA-Verilog] lut_core

Description: LUT core in VHDL program
Platform: | Size: 2048 | Author: xyz002 | Hits:

[VHDL-FPGA-Verilog] atan_lut

Description: atan LUT in VHDL program
Platform: | Size: 1024 | Author: xyz002 | Hits:

[VHDL-FPGA-Verilog] FIR-FILTER

Description: FIR filter LUT based in vhdl
Platform: | Size: 217088 | Author: sat | Hits:

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