Search - mATLAB TO VHDL

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[VHDL-FPGA-Verilog] dds正弦发生器代码 DL : 0: 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output
Update : 2025-02-19 Size : 480kb Publisher : czy
[Other] mif DL : 0: 使用metlab生产正弦波和三角波的采样值，供vhdl等语言调用来产生波形-use metlab production sine wave and triangular wave of sampling, for languages such as call vhdl to generate waveforms
Update : 2025-02-19 Size : 1kb Publisher : feng
[assembly language] GMSK_matlab DL : 0: gmsk的matlab实现，可直接运行，自己编写的，请高手指点！-GMSK matlab to achieve the direct running, I have written, please expert advice!
Update : 2025-02-19 Size : 3kb Publisher : 程林强
[VHDL-FPGA-Verilog] simulink-03-31 DL : 0: 基于MATLAB/DSP Ｂuild可控信号发生器，由Ｍatlab建模综合，并生成ＶＨＤＬ代码，由Ｑuartus编译通过．-Based on MATLAB/DSP Build controllable signal generator, by the Matlab modeling synthesis, and generates VHDL code, adopted by the Quartus compiler.
Update : 2025-02-19 Size : 291kb Publisher : ltianyang
[matlab] zigbee(matlab) DL : 0: 在matlab实现的zigbee源代码，并有相关论文做描述，比较全面-Zigbee achieved in the matlab source code, and have the relevant papers to do a description of a more comprehensive
Update : 2025-02-19 Size : 716kb Publisher : fgj
[Books] ise_9.01shiyong DL : 0: 本章详细介绍了基于ISE的FPGA设计流程以及多个辅助工具（XST、XPower、PACE、ModelSim、Synplify以及MATLAB）的使用方法。首先介绍了ISE软件主要特性及其安装流程，然后介绍了如何通过ISE完成FPGA设计，-This chapter details the FPGA-based ISE design flow, as well as a number of auxiliary tools (XST, XPower, PACE, ModelSim, Synplify, and MATLAB) to use. First introduced the main features of ISE software and its installation process, and then describes how the adoption of ISE complete FPGA design,
Update : 2025-02-19 Size : 7.29mb Publisher : 马军辉
[matlab] ddc DL : 0: 数字下变频器的matlab实现，一定的设计指标，可以用来知道vhdl程序设计-Digital Down Converter for matlab realized, certain design specifications that can be used to know VHDL Programming
Update : 2025-02-19 Size : 2kb Publisher : 杨斌
[VHDL-FPGA-Verilog] VHDL-ROM4 DL : 0: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Update : 2025-02-19 Size : 96kb Publisher : 宫逢源
[Software Engineering] matlab_to_vhdlfpga DL : 0: 　　本文提出了加快发展之路　　从理论设计,通过Matlab / Simulink环境　　在定点算法对其行为模拟的　　在FPGA或定制实现硅片。这个了　　实现了netlist移植的Simulink系统　　描述成的硬件描述语言[VHDL]。在这个例子中,这个　　Simulink-to-VHDL转换器被设计来使用　　代码来描述结构VHDL系统互连, 　　允许简单的行为说明基本模块。　　结果VHDL bit-true交付后代码　　比较定点Simulink仿真模型等效　　模拟。-This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.
Update : 2025-02-19 Size : 144kb Publisher : 王晓
[Software Engineering] acceldsp1 DL : 0: this the documentation of accel dsp software for dsp matlab to vhdl core
Update : 2025-02-19 Size : 116kb Publisher : ashkan
[DSP program] fir DL : 0: 先用matlab得到所需滤波器的系数，将AD采样的数据经过fir滤波器后输出-First to use matlab to obtain the required filter coefficients, data from the AD sample, after the output filter through the fir
Update : 2025-02-19 Size : 2.16mb Publisher : 潘存华
[matlab] aes DL : 0: Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
Update : 2025-02-19 Size : 8kb Publisher : allen
[Program doc] FULLTEXT01 DL : 0: viterbi thesis. it contains how to design viterbi decoding algorithm with matlab and vhdl code for g[171,133]
Update : 2025-02-19 Size : 563kb Publisher : ubi
[Other] sift-0[1].9.18.tar DL : 0: 用sift算法进行图像的匹配。可以两幅不同的图像中进行点对点的匹配。很好的图像匹配的算法。用matlab编程-Using sift algorithm for image matching. Two different images can be carried out point to point matching. A very good image matching algorithms. Programming using matlab
Update : 2025-02-19 Size : 2.75mb Publisher : liuyinghong
[Embeded-SCM Develop] DSP_Algorithms DL : 0: 基于FPGA的DSp算法转换方法-由matlab程序转换为VHDL-FPGA-based algorithm for DSp conversion method- from the matlab program is converted to VHDL
Update : 2025-02-19 Size : 144kb Publisher : dtcxh
[Mathimatics-Numerical algorithms] fir_filter DL : 0: 该数字滤波器通过结合matlab和vhdl来实现低通fir数字滤波器功能-The digital filter through a combination of matlab and vhdl to achieve low-pass digital filter function fir
Update : 2025-02-19 Size : 26kb Publisher : caoge
[VHDL-FPGA-Verilog] Simulink-to-VHDL-Route DL : 0: This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.-This paper presents the way of speeding up the route from the theoretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting the netlist of the Simulink system description into the VHDL. At the first instance, the Simulink-to-VHDL converter has been designed to use structural VHDL code to describe system interconnections, allowing simple behavioral descriptions for basic blocks. The resulting VHDL code delivers bit-true result when compared to the equivalent fixed-point Simulink model simulations.
Update : 2025-02-19 Size : 144kb Publisher : jack
[VHDL-FPGA-Verilog] 3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r DL : 0: Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
Update : 2025-02-19 Size : 144kb Publisher : T. H. Sutikno
[VHDL-FPGA-Verilog] matlab-gmsk DL : 1: 基于matlab和vhdl的通信原理gmsk调制算法，主要包括GMSK相位路径的计算,GMSK眼图的仿真以验证相位计算的正确性,正余弦表的量化及bin文件的生成,以及用VHDL硬件语言所描述的基于EPM7128的地址逻辑.-Matlab and vhdl based on the principle gmsk Modulation of communication, including GMSK phase path calculation, GMSK eye diagrams of the simulation to verify the correctness of the phase calculation, is the cosine table generating quantitative and bin files, and using VHDL hardware description language logic based on the address of EPM7128.
Update : 2025-02-19 Size : 450kb Publisher : zenpging
[VHDL-FPGA-Verilog] simulink-matlab-to-vhdl DL : 0: convert matlab and simulink files to vhdl
Update : 2025-02-19 Size : 177kb Publisher : tatta

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