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[VHDL-FPGA-Verilogm_vhdl

Description: 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器,采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值(程序中设定好四种非零初值可选)-m sequence vhdl
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilogm_vhdl

Description: 设计一个伪随机序列发生器,采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值(程序中设定好四种非零初值可选)。-Design a pseudo-random sequence generator, using the generating polynomial 1+ X ^ 3+ X ^ 7. Requires a RESET terminal end and two control registers to adjust the initial value (the program of four non-zero initial value set a good option).
Platform: | Size: 1024 | Author: haodiangei | Hits:

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