Description: 采用匹配滤波，实现伪码捕获功能，模块内部可以产生简单噪声来验证捕获性能(verilog)-Matched filter used to achieve pseudo-code capture functionality, the module can generate simple internal noise to verify the performance capture (verilog) Platform: |
Size: 2673664 |
Author:曹旸 |
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Description: Vhdl实现扩频通信匹配滤波器，书上打下来的,打了好久.-VHDL realization of spread spectrum communication matched filter, books, playing down, playing for a long time. Platform: |
Size: 1024 |
Author:刘小姐 |
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Description: 这是一个非常完整的qpsk调制解调用fpga实现的工程，在工程中已经能够正常使用，使用的quartus ii 开发，使用Verilog语言，文件中还包含了各种滤波器的系数文件，还有matlab仿真文件，整个工程包含从串并变换，相位映射，到成型滤波，中通滤波，cic滤波，调制，再到解调过成的下变频，匹配滤波，载波提取，位定时，判决，整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implementation of the project, the project has been able to properly use the Quartus II development, the use of Verilog language, the file also contains the files of various filter coefficients, and MATLAB simulation files, including the entire project from the string and transform, phase mapping, molding in filtering, filtering, CIC filtering, modulation, and demodulation frequency, a matched filter, carrier extraction, timing, judgment, the whole course) Platform: |
Size: 13488128 |
Author:maerzaizai |
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