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[VHDL-FPGA-Verilog] color_converter.tar

Description: 此代码实现不同图像颜色制式之间的相互转换，如XYZ<->RGB, 不同标准的RGB<->RGB 以及RGB<->YCbCr之间的转换，包内含有matlab仿真代码m文件、VHDL代码.v文件以及modelsim仿真的testbench文件，相信对大家有一定的帮助-This code different image color conversion between formats, such as XYZ <-> RGB, different standards of RGB <-> RGB and RGB <-> YCbCr conversion between packet contains code m file matlab simulation, VHDL code . v documents and ModelSim Simulation Testbench documentation, I believe everyone will certainly help
Platform: | Size: 339968 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] fibonacci_matlab_verilog

Description: 使用Matlab和Verilog实现fibonacci序列，包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
Platform: | Size: 229376 | Author: fc | Hits:

[VHDL-FPGA-Verilog] FIR_matlab

Description: 使用ｍａｔｌａｂ的ｆｄａｔｏｏｌ工具生成的ＶｅｒｉｌｏｇＦＩＲ滤波器代码，自带测试ｔｅｓｔｂｅｎｃｈ-The the Matlab fdatool tool to generate VerilogFIR filter code, self-testing testbench
Platform: | Size: 628736 | Author: 海峰 | Hits:

[VHDL-FPGA-Verilog] matlab-and-verilog-fir4_3

Description: 四抽头FIR滤波器matlab,verilog顶层，子模块，以及testbench代码-Four tap FIR filter matlab, verilog top, sub modules, as well as the testbench code
Platform: | Size: 8192 | Author: 李静 | Hits:

[VHDL-FPGA-Verilog] ADC_Data_Recv_Module

Description: 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated data The compressed package includes the Verilog code, the testbench code Matlab simulation code)
Platform: | Size: 512000 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] Clock_Synchronization_Module

Description: 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
Platform: | Size: 245760 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] FFT_Module

Description: 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Platform: | Size: 6002688 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] Orthogonization_Module

Description: 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
Platform: | Size: 1798144 | Author: nokkk | Hits:

[VHDL-FPGA-Verilog] CIC_Filter_Module

Description: 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
Platform: | Size: 3013632 | Author: nokkk | Hits:

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