Search - matrix verilog

[Other] LDPC

Description: 用于LDPC编码译码的仿真实现。包括随机生成校验矩阵、由校验矩阵产生生成矩阵、编码、加随机噪声、译码等内容。原作者是老外，有部分中文注释。-LDPC coding for decoding Simulation. Check including random matrix generated by the calibration matrix generated generator matrix, coding, plus random noise, such as decoding. The original author is a foreigner, some Chinese Notes.
Platform: | Size: 58368 | Author: 别志松 | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] lcd4quartus

Description: 128×64单色点阵LCD的quartus工程文件-128 x 64 monochrome dot-matrix LCD quartus works documents
Platform: | Size: 703488 | Author: HYP | Hits:

[VHDL-FPGA-Verilog] NumClock

Description: 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。-based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design
Platform: | Size: 23552 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] key

Description: 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
Platform: | Size: 199680 | Author: 林虎 | Hits:

[Multimedia program] dct

Description: Mpeg2视频压缩时进行空间压缩时的离散余弦变换矩阵的verilog实现，采用modelsim验证-Mpeg2 video compression when space compression of discrete cosine transform matrix realize Verilog using ModelSim verification
Platform: | Size: 29696 | Author: mayang | Hits:

[VHDL-FPGA-Verilog] jianpan

Description: 这是我用verilog语言编写的矩阵键盘源程序 -This is what I use Verilog language source matrix keyboard
Platform: | Size: 1024 | Author: hejunbo | Hits:

[Communication-Mobile] f2

Description: 96位矩阵循环乘法，verilog实现，-96 matrix multiplication cycle, verilog realized,
Platform: | Size: 1024 | Author: 王佳 | Hits:

[VHDL-FPGA-Verilog] integrity

Description: 用DE2板子实现的控制64乘64点阵LED的点亮,硬件需要de2板及led点阵-Using DE2 realize the control board 64 x 64 dot matrix LED
Platform: | Size: 1567744 | Author: 任迎 | Hits:

[VHDL-FPGA-Verilog] 3_4×4

Description: verilog 键盘输入程序，用于led灯的显示-Verilog keyboard input program for led lights display
Platform: | Size: 627712 | Author: tang | Hits:

[VHDL-FPGA-Verilog] 11

Description: verilog 任意维矩阵求逆的verilog实现方式-Verilog arbitrary-dimensional matrix inversion methods to achieve the Verilog
Platform: | Size: 202752 | Author: 付彦青 | Hits:

[3G develop] H_512x1024

Description: LDPC 码二进制规则码生成矩阵512*1024，效果很理想-LDPC code rules binary code matrix to generate 512* 1024, the effect is very satisfactory
Platform: | Size: 9216 | Author: wwwwomen | Hits:

[3G develop] H_2048x4096

Description: LDPC 码二进制规则码生成矩阵2048*4096，效果很理想-LDPC code rules binary code generated matrix 2048* 4096, the effect is very satisfactory
Platform: | Size: 56320 | Author: wwwwomen | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[VHDL-FPGA-Verilog] VerilogHDL44keyboard

Description: verilog hdl 4*4 矩阵键盘，去抖-verilog hdl 4* 4 matrix keyboard, to tremble
Platform: | Size: 39936 | Author: 黎德才 | Hits:

[File Format] SDH

Description: FPGA的应用，数字交叉连接矩阵的应用，VERILOG的一些应用等-FPGA applications, the application of digital cross-connect matrix, VERILOG some of the applications
Platform: | Size: 707584 | Author: 辛晨 | Hits:

[VHDL-FPGA-Verilog] IDCT

Description: 用verilog HDL语言编写的IDCT程序，可以计算8*8的整形数矩阵，用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
Platform: | Size: 479232 | Author: 阿文 | Hits:

[VHDL-FPGA-Verilog] matrix3x3

Description: 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
Platform: | Size: 4096 | Author: wjlsomeone | Hits:

[Software Engineering] gaijinjuzhenqiuniFPGA

Description: 改进的矩阵求逆的FPGA设计和实现（文章）感觉写得很不错-Improved matrix inversion of the FPGA design and implementation (article) wrote very good feeling
Platform: | Size: 247808 | Author: lq | Hits:

[VHDL-FPGA-Verilog] Realization_of_FPGA_for_LDPC_encoding

Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC code．
Platform: | Size: 165888 | Author: 秦小星 | Hits:

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