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[GUI Develop] MAX_II_board_schematics.pdf DL : 0: MAXII开发板原理图． Revision Index & Table of Contents MAX II and Pereipherals PCI USB and Power Supplies Prototyping Area-MAXII development board schematics. Revision Index
Update : 2008-10-13 Size : 235.65kb Publisher : 赵天
[Other resource] MAX_II_board_schematics DL : 0: Altera MAX II 开发板原理图-Altera's MAX II development board schematics
Update : 2008-10-13 Size : 235.97kb Publisher : 吴军
[Other resource] CPLDxiaoche DL : 0: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Update : 2008-10-13 Size : 1.34kb Publisher : lili
[Applications] C_10 DL : 0: VHDL实例,在MAX+Plus+II下开发-VHDL example, the MAX II Plus under development
Update : 2008-10-13 Size : 1.22mb Publisher : 孙庆波
[Other resource] an485_design_example DL : 0: AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）
Update : 2008-10-13 Size : 305.25kb Publisher : zhiqiang
[Software Engineering] Max+Plus-II_Quickstart_Chinese DL : 0: Max+Plus II 简易用户使用入门指南
Update : 2008-10-13 Size : 229.08kb Publisher : whr
[Embeded-SCM Develop] MaxPlus ii 的初次使用 DL : 0: MaxPlus ii 的初次使用--Use MaxPlus iii for the first time.
Update : 2025-02-17 Size : 362kb Publisher : 李明
[Books] max+plus ii快速入门 DL : 0: maxplus2是一款应用于硬件编程的编程软件，本文件教你快速掌握其编程，仿真方法。-maxplus2 hardware is a programming application programming software, this document will teach you grasp its programming and simulation methods.
Update : 2025-02-17 Size : 336kb Publisher : 刘晓飞
[GUI Develop] MAX_II_board_schematics.pdf DL : 0: MAXII开发板原理图． Revision Index & Table of Contents MAX II and Pereipherals PCI USB and Power Supplies Prototyping Area-MAXII development board schematics. Revision Index
Update : 2025-02-17 Size : 235kb Publisher : 赵天
[VHDL-FPGA-Verilog] MAX_II_board_schematics DL : 0: Altera MAX II 开发板原理图-Altera's MAX II development board schematics
Update : 2025-02-17 Size : 236kb Publisher : 周宇
[Software Engineering] Max+Plus-II_Quickstart_Chinese DL : 0: Max+Plus II 简易用户使用入门指南-Max+ Plus II Simple User Getting Started Guide
Update : 2025-02-17 Size : 229kb Publisher : whr
[VHDL-FPGA-Verilog] FT245BM DL : 0: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言-This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Update : 2025-02-17 Size : 953kb Publisher : 杨林成
[Software Engineering] MAXII_application_handbook(chinese) DL : 0: MAX II CPLD具有灵活的可编程接口，合并了分立的FLASH存储器件，能快速和容易地配置FPGA，DSP，ASIC等。本中文手册将让用户对CPLD有一个宏观的认识。-MAX II CPLD with a flexible programmable interface, the merger of the separation of FLASH memory, can quickly and easily configure the FPGA, DSP, ASIC, etc.. Chinese manual will allow users to have a macro on the CPLD awareness.
Update : 2025-02-17 Size : 967kb Publisher : pantree
[File Format] Quartus DL : 0: Quartus II 是Altara公司继MAX II之后开发的新软件，很适合做FPGA的开发。-Quartus II is Altara after the company following the MAX II development of new software, it is suitable for FPGA development.
Update : 2025-02-17 Size : 825kb Publisher : cathy
[VHDL-FPGA-Verilog] MAX_II_examples_of_internal_shocks_clock DL : 0: BJ-EPM240V2实验例程以及说明文档实验之十三MAX II内部震荡时钟实例-BJ-EPM240V2 experimental test routines as well as documentation of the MAX II 13 examples of internal shocks clock
Update : 2025-02-17 Size : 450kb Publisher : 王建毅
[VHDL-FPGA-Verilog] MAX_II_using_the_example_of_the_UFM_block DL : 0: BJ-EPM240V2实验例程以及说明文档实验之十四MAX II的UFM模块使用实例-BJ-EPM240V2 experimental test routines as well as documentation of the MAX II 14 UFM module uses examples
Update : 2025-02-17 Size : 723kb Publisher : 王建毅
[Documents] an428 DL : 0: MAX II CPLD 设计手册英文版-MAX II CPLD Design Guidelines
Update : 2025-02-17 Size : 278kb Publisher : shufeng
[VHDL-FPGA-Verilog] fir-filter-design-using-fpga-with-MAX-Plus2 DL : 1: 基于FPGA的高阶FIR滤波器设计用max-plus　－II软件仿真-fir filter using fpga with max-plusII
Update : 2025-02-17 Size : 2.23mb Publisher : 星空心晴之夏
[Other] Using-the-Internal-Oscillator-in-MAX-II-CPLDs DL : 0: MAX® II devices have an internal oscillator as part of the user flash memory (UFM). The internal oscillator can be used to meet the clocking requirements of many designs and eliminate the requirement for an external clock circuitry. This application note describes the instantiation of the internal oscillator and its usage.-MAX® II devices have an internal oscillator as part of the user flash memory (UFM). The internal oscillator can be used to meet the clocking requirements of many designs and eliminate the requirement for an external clock circuitry. This application note describes the instantiation of the internal oscillator and its usage.
Update : 2025-02-17 Size : 213kb Publisher : kiam
[VHDL-FPGA-Verilog] an496_design_example DL : 0: MAX II that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some. ers that having account in so they can help you to get your files. But to prevent overloading and abusing; We have some.
Update : 2025-02-17 Size : 229kb Publisher : yellowhataq

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