Search - max plus 2

[Other resource] vhdl-2

Description: UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
Platform: | Size: 59976 | Author: lileiming | Hits:

[Other resource] electric_bell

Description: 电子打铃器在max plus 2 下编译通过-electronic bell playing for the max plus 2 under through compiler
Platform: | Size: 13902 | Author: wenquan | Hits:

Description: maxplus2是一款应用于硬件编程的编程软件，本文件教你快速掌握其编程，仿真方法。-maxplus2 hardware is a programming application programming software, this document will teach you grasp its programming and simulation methods.
Platform: | Size: 344064 | Author: 刘晓飞 | Hits:

[CSharp] pof2jed

Description: MAX+PLUS II 生成pof文件到Atmel15xx系列jed下载格式的转换软件windows版。-MAX PLUS II generation POF documents to the Atmel15xx series jed download format windows version of the software conversion.
Platform: | Size: 1270784 | Author: yibu | Hits:

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[VHDL-FPGA-Verilog] electric_bell

Description: 电子打铃器在max plus 2 下编译通过-electronic bell playing for the max plus 2 under through compiler
Platform: | Size: 13312 | Author: wenquan | Hits:

[Documents] 040207

Description: 数字钟电路系统由主体电路和扩展电路两大部分组成。其中，主体电路完成数字钟的基本功能，扩展电路完成数字钟的扩展功能。用MAXPLUSⅡ进行电路设计与仿真.-digital clock circuit system from the main circuit and the circuit extended two major components. Among them, the main circuit digital clock to complete the basic functions, expanding digital clock circuit to complete the expansion function. II FPGA used for circuit design and simulation.
Platform: | Size: 455680 | Author: 李明 | Hits:

[Other] MAXPLUS

Description: Altera公司的max+plus2软件的详细使用演示,从入门到精通-Altera's max plus2 use of the detailed software demonstrations, from entry level to proficiency
Platform: | Size: 262144 | Author: 苏航 | Hits:

[Software Engineering] maxplus2shizishizhong

Description: 数字电子钟的设计（二十四小时六十分钟六十秒）-digital electronic clock design (24 hours 60 minutes 60 seconds)
Platform: | Size: 500736 | Author: yan | Hits:

[Software Engineering] MAX+plus2

Description: maxplus_2的入门书籍，对刚接触maxplus的朋友很有帮助。希望对大家有所帮助-maxplus_2 entry books,刚接触maxplus of helpful friends. I hope all of you to help
Platform: | Size: 20413440 | Author: 方文利 | Hits:

[Embeded-SCM Develop] EDA12

Description: EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的MAX+PLUS-EDA applications. QUARTUES II with EDA technology to achieve the experimental operation, similar to the classical MAX+ PLUS
Platform: | Size: 3998720 | Author: 曾伟 | Hits:

[Software Engineering] 07302529

Description: 计算机组成原理实验（MAX PLUS） 1.ALU设计 2.MEM设计 3.32位2选1选择器-Principles of Computer Organization Experiment (MAX PLUS) 1.ALU design 2.MEM design 3.32 2 election 1 selector
Platform: | Size: 244736 | Author: 翁浩达 | Hits:

[SCM] MAXplusIICrack

Description: MAX+plus II FPGA CPLD开发软件完美无限制破解版-MAX+ plus II FPGA CPLD development software cracked unlimited version of the perfect
Platform: | Size: 134144 | Author: 吴玉保 | Hits:

[Books] EDA

Description: 介绍使用MAX+plus 2以及部分实验原理介绍，以及EDA开发工具。-On the use of MAX+ plus 2, as well as to introduce the principle part of the experiment, and the EDA development tools.
Platform: | Size: 657408 | Author: 徐婷婷 | Hits:

[Other] EDA

Description: 基于MAX PLUS 2 FPGA 依据状态机结构的10禁止计数器内附其仿真图-MAX PLUS 2 FPGA based state machine based on the structure of the 10 counter containing the prohibition of the simulation map
Platform: | Size: 11264 | Author: yuqingwei | Hits:

[Other] quartus2

Description: 您现在阅读的是 Quartus II 简介手册。 Altera® Quartus® II 设计软件是适合单芯片可编程系统 (SOPC) 的最全面的设计环境。如果您以前用过 MAX+PLUS® II 软件、其它设计软件或 ASIC 设计软件，并且准备改用 Quartus II 软件，或如果您对 Quartus II 软件有了一些了解但想进一步了解它的功能，那么本手册非常适合您。 -You are now reading the Quartus II brochure. Altera ® Quartus ® II design software is suitable for single-chip programmable system (SOPC) the most comprehensive design environment. If you have previously used the MAX+ PLUS ® II software, ASIC design software or other design software, and is prepared to use Quartus II software, or if you have some idea of Quartus II software, but would like to learn more about its capabilities, then this manual is for you.
Platform: | Size: 3096576 | Author: 倪萍波 | Hits:

[Compress-Decompress algrithms] vote7

Description: 七人表决 MAX + PLUS 2 编写 -Seven people to vote
Platform: | Size: 44032 | Author: wang | Hits:

[Other] 100vhdlsimple

Description: 100个vhdl例子，对初学者很有用，可以用MAX+PLUS 2来编译仿真的-100 vhdl example, useful for beginners, you can use the MAX+ PLUS 2 to compile the simulation
Platform: | Size: 233472 | Author: 刘超 | Hits:

[JSP/Java] jsweixindfj

Description: 纯JavaScript模仿微信打飞机游戏，做网页小游戏的借鉴下，界面设计是竖长形仿手机屏幕风格，游戏效果流畅。具有分数统计，里面的JS封装类中包括有创建飞机类、飞机移动行为控制，创建子弹类，产生min到max之间的随机数，判断本方飞机是否移出边界,如果移出边界,则取消mousemove事件,反之加上mousemove事件，为暂停界面的继续按钮添加暂停事件，创建敌方飞机类、碰撞判断、完成界面的初始化，敌方小飞机一个，我方飞机一个-Pure JavaScript to mimic the micro-channel planes games, web games do reference, interface design is an elongated vertical screen style imitation mobile phone, game results and smooth. Have fractional statistics, which the JS wrapper classes include classes created aircraft, aircraft control movement behavior, create bullet classes, random number generation min to max between the aircraft to determine whether the party out of the boundaries, if removed the border, then canceled mousemove event, whereas plus mousemove event, adding to continue pause button to pause interface events, create class enemy aircraft, collision judgment, complete interface initialization, the enemy of a small plane, one of our aircraft
Platform: | Size: 233472 | Author: lpudn81 | Hits:

« 12 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list