Search - max plus vhdl

[Other resource] vhdl-2

Description: UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
Platform: | Size: 59976 | Author: lileiming | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269899 | Author: 王越 | Hits:

[Other resource] taxi-vhdl

Description: 出租车计费器硬件描述语言出租车计费器 MAX+PLUS软件数字系统
Platform: | Size: 48424 | Author: aneeee | Hits:

[midi program] Music

Description: MAX plus VHDL语言实现音乐的演奏
Platform: | Size: 4369 | Author: gjx | Hits:

Description: 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin
Platform: | Size: 865280 | Author: 田晶昌 | Hits:

[VHDL-FPGA-Verilog] Booth_Multiplier

Description: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Platform: | Size: 1024 | Author: 韓堇 | Hits:

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] VHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] DigitalClockVHDL

Description: 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
Platform: | Size: 83968 | Author: wangyiran | Hits:

[Program doc] MAX+plusIIxiaVHDLsheji

Description: VHDL在MAX+plusII下进行的电路设计!是一个WORD文档!-VHDL in MAX+ PlusII carried out under the circuit design! Is a WORD document!
Platform: | Size: 12288 | Author: 段正伟 | Hits:

[VHDL-FPGA-Verilog] taxi-vhdl

Description: 出租车计费器硬件描述语言出租车计费器 MAX+PLUS软件数字系统-Taxi billing hardware description language taxi meter MAX+ PLUS software digital systems
Platform: | Size: 48128 | Author: aneeee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 《VDHL硬件描述语言与数字逻辑》 ——————电子工程师必备知识西安电子科技大学出版社出版第一章数字系统硬件设计概述第二章 VHDL语言程序的基本结构第三章 VHDL语言的数据类型及运算操作符第四章 VHDL语言构造体的描述方式第五章 VHDL语言的主要描述语言第六章数值系统的状态模型第七章基本逻辑电路设计第八章仿真与逻辑综合第九章计时电路设计实例第十章微处理器接口芯片设计实例第十一章 93版和87版VHDL语言的主要区别第十二章 MAX+plusII使用说明
Platform: | Size: 18693120 | Author: 陈松 | Hits:

[midi program] Music

Description: MAX plus VHDL语言实现音乐的演奏-MAX plus VHDL language music recital
Platform: | Size: 4096 | Author: gjx | Hits:

[VHDL-FPGA-Verilog] electoniclock

Description: 摘　要: 数字密码锁主要完成上锁、密码输入、密码核对、开启电锁、密码修改等功能.数字密码锁的设计电路主要包括 11 个模块 ,各模块由相应的 VHDL 程序具体实现并分别进行了 MAX + PLUS II 时序仿真. 最后 ,在 MAX + PLUS Ⅱ环境下进行了整体电路的模拟仿真 ,结果表明 ,整个设计满足要求.
Platform: | Size: 712704 | Author: 孙光华 | Hits:

[VHDL-FPGA-Verilog] 0097

Description: MAX+plus II编译的模30加法计数器，简单的与非门组成！-MAX+ Plus II compiler module adder 30 counters, a simple composition with the non-door!
Platform: | Size: 13312 | Author: LEE | Hits:

[VHDL-FPGA-Verilog] MAX-PLUSII-soft

Description: MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input methods (AHDL, VHDL and VERILOG) and waveform enter design documents can be compiled and form can be downloaded to a variety of EPROM and ALTERA documents a variety of devices can also be used for simulation to test the accuracy of the design, the following examples to illustrate the use of the software
Platform: | Size: 124928 | Author: 徐靖 | Hits:

[VHDL-FPGA-Verilog] WATERHOURMETERBASEDONVHDL

Description: 在 MAX+PLUS II开发环境下采用 VHDL语言设计并实现了电表抄表器讨论了系统的四个组成模块的设计和 VHDL 的实现每个模块采用 RTL 级描述整体的生成采用图形输入法通过波形仿真下载芯片测试完成了抄表器的功能-In the MAX+ PLUS II development environment using VHDL language design and implementation of the meter meter reading device to discuss the four components of the system module design and VHDL implementation of each module using RTL-level description of a whole generation of graphical input waveform Simulation download chip testing completed meter reading functions
Platform: | Size: 239616 | Author: linfeng | Hits:

[VHDL-FPGA-Verilog] MaxplusII

Description: 本电子书详细地介绍了VHDL语言开发环境 Max+plus II 软件的使用方法，让新手很快学会如何使用本软件-This book describes in detail VHDL language development environment Max+ plus II software to use, so that novices will soon learn how to use the software
Platform: | Size: 1048576 | Author: may | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

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[Other resource] vhdl-2

[Other] VHDL-FPGA-clock

[Other resource] taxi-vhdl

[midi program] Music

[VHDL-FPGA-Verilog] maxshiyan

[VHDL-FPGA-Verilog] Booth_Multiplier

[VHDL-FPGA-Verilog] vhdl-2

[VHDL-FPGA-Verilog] VHDL-Clock

[Other] VHDL-FPGA-clock

[VHDL-FPGA-Verilog] DigitalClockVHDL

[Program doc] MAX+plusIIxiaVHDLsheji

[VHDL-FPGA-Verilog] taxi-vhdl

[VHDL-FPGA-Verilog] VHDL

[midi program] Music

[VHDL-FPGA-Verilog] electoniclock

[VHDL-FPGA-Verilog] 0097

[VHDL-FPGA-Verilog] MAX-PLUSII-soft

[VHDL-FPGA-Verilog] WATERHOURMETERBASEDONVHDL

[VHDL-FPGA-Verilog] MaxplusII

[Software Engineering] vhdl-TAXI

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