Search - max plusii

[Other resource] SECLOCK

Description: 我从一本书上抄来的但用MAX+PLUSII编译有些问题初学者见谅-from a book copied but with the MAX PLUSII compile some of the problems beginners forgiven
Platform: | Size: 3908 | Author: male | Hits:

[Other resource] 基于FPGA的李沙育图形发生器

Description: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Platform: | Size: 791509 | Author: 孔玉 | Hits:

[Other resource] zldjkzjq

Description: max+plusII下编成的直流电机控制器vhd-under monument of the DC motor controller vhd
Platform: | Size: 2669 | Author: 李清 | Hits:

[Other resource] ztj

Description: max+plusII下的使用列举类型的状态机-max plusII use of the listed types of state machine.
Platform: | Size: 1434 | Author: 李清 | Hits:

[Other resource] jcq

Description: max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
Platform: | Size: 1135 | Author: 李清 | Hits:

[Other resource] pingpangqiu

Description: 用max+plusII编写的vhdl程序乒乓球游戏机-with max plusII vhdl procedures for the preparation of the table tennis game
Platform: | Size: 14545 | Author: 黄还 | Hits:

[Other resource] count_usebasketball

Description: 一个小程序，用Veilog HDL编写的，可以用于篮球比赛的倒计时牌，已在max-plusII上仿真通过。-a small program, prepared by the Veilog HDL, can be used for the basketball game countdown. have max-plusII on through simulation.
Platform: | Size: 2202 | Author: 孙忠诚 | Hits:

[File Operate] MAX+PLUSII

Description: MAX+PLUSII不错的电子书,内容详细,易懂.-MAX PLUSII good e-books, detailed, understandable.
Platform: | Size: 262539 | Author: zhoudefang | Hits:

[Communication] MAX+plusIIxiaVHDLsheji

Description: VHDL在MAX+plusII下进行的电路设计!是一个WORD文档!
Platform: | Size: 12445 | Author: 段正伟 | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的李沙育图形发生器

Description: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Platform: | Size: 791552 | Author: 孔玉 | Hits:

[VHDL-FPGA-Verilog] chengxufengxiang

Description: 这些程序我用MAX+PlusII软件测试均能通过编译，程序本身不复杂，旨在为刚接触VHDL语言的朋友提供一些样例，以便了解VHDL语言的基本构成。如果要运行测试，则新建文件名应于程序中实体名一致，文件后缀“.vhd”，不推荐直接通过复制、粘贴的方法录入程序，可能会引入错误字符。 -these procedures I used MAX PlusII Software Testing pass compiler, the process itself is not complicated. for the fourth year to VHDL friend to provide some examples in order to understand the VHDL basic components. If testing, the new file name in the process should be entity line extensions. " Vhd " not recommended directly by copying and pasting the time of admission procedures, the potential introduction of the wrong characters.
Platform: | Size: 1024 | Author: zhaoting | Hits:

[File Format] MAX+PLUSII

Description: MAX+PLUSII不错的电子书,内容详细,易懂.-MAX PLUSII good e-books, detailed, understandable.
Platform: | Size: 262144 | Author: zhoudefang | Hits:

[Program doc] MAX+plusIIxiaVHDLsheji

Description: VHDL在MAX+plusII下进行的电路设计!是一个WORD文档!-VHDL in MAX+ PlusII carried out under the circuit design! Is a WORD document!
Platform: | Size: 12288 | Author: 段正伟 | Hits:

[VHDL-FPGA-Verilog] myproject

Description: 四位全加器，VHDL语言，max+plusII平台做的-Four full-adder, VHDL language, max+ PlusII platform to do
Platform: | Size: 56320 | Author: 邱飞 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 《VDHL硬件描述语言与数字逻辑》 ——————电子工程师必备知识西安电子科技大学出版社出版第一章数字系统硬件设计概述第二章 VHDL语言程序的基本结构第三章 VHDL语言的数据类型及运算操作符第四章 VHDL语言构造体的描述方式第五章 VHDL语言的主要描述语言第六章数值系统的状态模型第七章基本逻辑电路设计第八章仿真与逻辑综合第九章计时电路设计实例第十章微处理器接口芯片设计实例第十一章 93版和87版VHDL语言的主要区别第十二章 MAX+plusII使用说明
Platform: | Size: 18693120 | Author: 陈松 | Hits:

[VHDL-FPGA-Verilog] MAX-PLUSII-soft

Description: MAX+PLUSII软件是一个功能强大，容易使用的软件包，它可以以图形方式、文字输入方式（AHDL、VHDL和VERILOG）和波形方式输入设计文件，可以编译并形成各种能够下装到EPROM和各种ALTERA器件的文件，还可以进行仿真以检验设计的准确性，下面举例说明该软件的使用-MAX+ PLUSII software is a powerful, easy-to-use software package, which can graphically, text input methods (AHDL, VHDL and VERILOG) and waveform enter design documents can be compiled and form can be downloaded to a variety of EPROM and ALTERA documents a variety of devices can also be used for simulation to test the accuracy of the design, the following examples to illustrate the use of the software
Platform: | Size: 124928 | Author: 徐靖 | Hits:

[Other] OP07_a

Description: The OP07 has very low input offset voltage (75 μV max for OP07E) which is obtained by trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (±4 nA for OP07E) and high open-loop gain
Platform: | Size: 194560 | Author: meyssam | Hits:

[Other] maxplus2

Description: 开发VHDL的工具，MAX+PLUSII 直接下载使用,-VHDL development tools, MAX+ PLUSII direct download,
Platform: | Size: 17325056 | Author: sunruili | Hits:

[VHDL-FPGA-Verilog] fir-filter-design-using-fpga-with-MAX-Plus2

Description: 基于FPGA的高阶FIR滤波器设计用max-plus　－II软件仿真-fir filter using fpga with max-plusII
Platform: | Size: 2334720 | Author: 星空心晴之夏 | Hits:

[VHDL-FPGA-Verilog] TAXI

Description: 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, control module, measuring module and decoding the display module, and finally use the MAX+ PLUSII software to simulate the program to simulate the realization of a taxi start, stop and wait for the timing of such processes, the meter and billing functions.
Platform: | Size: 1024 | Author: 张鹏飞 | Hits:

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