Search - mcp2515 can controller vhdl

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[VHDL-FPGA-Verilog] CAN_IP DL : 1: 这是CAN总线控制器的IP核，源码是由Verilog HDL编写的。其硬件结构与SJA1000类似，满足CAN2.0B协议。-This is a IP core of the CAN bus controller written by the Verilog HDL. whose structure is similar with SJA1000,supporting the protocol of CAN2.0B.
Update : 2025-02-17 Size : 60kb Publisher : 普林斯