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Description: 密码算法AES,DES,IDEA,MD5等的基本理论和硬件加速方案,对算法进行fpga硬件加速的优点等
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Size: 1817210 |
Author: 胡昊 |
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Description: MD5 算法在Xilinx FPGA上的实现,希望对大家有用。
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Size: 10490 |
Author: 张开文 |
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Description: 本代码是SHA1用C语言实现的源代码,SHA1与MD5是目前最为常用的HASH算法,可用于认证及签名等-This code is SHA1 with C language source code, SHA1 and MD5 is currently the most commonly used HASH algorithm, can be used for authentication and signatures
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Size: 53248 |
Author: cl |
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Description: 密码算法AES,DES,IDEA,MD5等的基本理论和硬件加速方案,对算法进行fpga硬件加速的优点等-Cryptographic algorithm AES, DES, IDEA, MD5, etc. The basic theory and hardware acceleration program, the algorithm of the advantages of FPGA hardware acceleration, etc.
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Size: 1816576 |
Author: 胡昊 |
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Description: MD5 算法在Xilinx FPGA上的实现,希望对大家有用。-MD5 algorithm in Xilinx FPGA Implementation, in the hope that useful to everyone.
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Size: 10240 |
Author: 张开文 |
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Description: FORFPGA IMPLEMENTATION OF RSA ALGORITHM USING HDL
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Size: 227328 |
Author: HIMANSHU SINGH |
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Description: MD5 Hash Algoritm implementation on a FPGA. Performance evaluation.
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Size: 119808 |
Author: Birrax |
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Description: 本人设计的一个基于FPGA平台用verilogHDL设计的MD5加密,供FPGA学习者学习参考-a MD5 encoder designed by me.It s a learning code for FPGA learner
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Size: 14491648 |
Author: Gevy |
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Description: MD5选择前缀碰撞关键技术研究
HASH,MD5,差分攻击算法,模差分,差分路径,FPGA,GPU,选择前缀碰撞
-The MD5 select prefix collisions key technology research
HASH, MD5 differential attack algorithm mode differential differential path, FPGAs, GPU, select the prefix collision
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Size: 1181696 |
Author: fj |
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Description: 哈希算法FPGA实现代码,采用MD5算法,并给出了仿真波形。-MD5 hashing algorithm for FPGA implementation code
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Size: 9216 |
Author: bigblue |
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Description: md5算法的vhdl实现,并配有测试用例,并没有使用任何xilinx的library,用modelsim se进行仿真-md5 algorithm based on fpga in vhdl
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Size: 5120 |
Author: Boxuan Li |
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Description: FPGA IMPLEMENTATION OF MD5 HASH ALGORITHM
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Size: 119808 |
Author: swapnil |
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Description: MD5认证部分的第一轮中包含F函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus II
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Size: 326656 |
Author: 柳广兴 |
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Description: MD5认证部分的第二轮中包含G函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-FPGA contains one operation in the second round of the G function MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
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Size: 321536 |
Author: 柳广兴 |
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Description: MD5认证部分的第三轮中包含H函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-FPGA third round included H functions in one operation MD5 authentication component implementation source code, using Verilog, synthesis in Quartus II
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Size: 295936 |
Author: 柳广兴 |
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Description: MD5认证部分的第四轮中包含I函数的一次操作的FPGA实现源代码,采用Verilog,在Quartus II上综合-The fourth round MD5 authentication section contains FPGA one operation I Functions of the source code, using Verilog, synthesis in Quartus II
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Size: 308224 |
Author: 柳广兴 |
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