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Description: 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data_valid,
input gtx_clk,
output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows:
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data
Platform: |
Size: 53248 |
Author: qiubin |
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