Description: 图像滤波中的中值滤波,有效滤除椒盐噪声,使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language Platform: |
Size: 3262464 |
Author:钱军 |
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Description: 3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。
-3x3 median filter FPGA implementation of the present (VERILOG) can be used directly. Platform: |
Size: 54272 |
Author:zenghui411 |
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Description: 中值滤波的FPGA(Verilog语言)实现方法,可以作为通信,图像专业的编程参考, -Median filter FPGA (Verilog language) implementation can be used as communication, professional programming reference image, Platform: |
Size: 2606080 |
Author:安靖宇 |
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Description: 实现图像的中值滤波功能,文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display) Platform: |
Size: 30031872 |
Author:gxgone |
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Description: 这个verilog程序实现了图像中值滤波,处理实时性很强,有兴趣的可以参考(This Verilog program implements the median filter in the image, the processing is very real, and the interest can be referred to) Platform: |
Size: 1950720 |
Author:zengang |
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