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[VHDL-FPGA-Verilog] frequency_meter_VHDL

Description: 一个用VHDL完成的8位数显的16进制的频率计-a VHDL completed 8 of 16 significant median band of frequency meter
Platform: | Size: 5120 | Author: 袁卫 | Hits:

[VHDL-FPGA-Verilog] fifo_01

Description: 8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn
Platform: | Size: 1024 | Author: 罗兰 | Hits:

[Special Effects] 2004041020082732202

Description: 对图像进行中值滤波处理的源代码,进行图像复原-right image median filtering of the source code, image recovery
Platform: | Size: 1024 | Author: bingo2003 | Hits:

[Algorithm] xfft16_beh_vhdl

Description: 能实现16位的快速傅立叶变化,位数可自由设定,输出斜波可调整个数-Can realize the fast Fourier 16 changes in the median can be free to set up, the output ramp adjustable number of
Platform: | Size: 152576 | Author: 胡召宇 | Hits:

[Communication-Mobile] CIC

Description: CIC梳妆滤波器生成器，生成任意位数任意长度的CIC滤波器源代码-Dressing CIC filter generator to generate any arbitrary length of the median of the CIC filter source code
Platform: | Size: 134144 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] mid-filter

Description: 用vhdl语言实现的中值滤波,硬件需要DE2板-VHDL language used to achieve the median filter, the hardware need to DE2 board
Platform: | Size: 1270784 | Author: 任迎 | Hits:

[VHDL-FPGA-Verilog] median

Description: 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
Platform: | Size: 1775616 | Author: yuming | Hits:

[VHDL-FPGA-Verilog] VHDL-SPI-Module.doc

Description: 本spi参数化通讯模块是一个支持SPI串行通信协议从协议的SPI从接口。可通过改变参数设置传输的位数，由外部控制器给定脉冲控制传输。-The parameters of spi communication module is a support SPI serial communication protocol from the agreement from the SPI interface. By changing the parameter settings can be transmitted over the median, given by an external controller to control transmission pulse.
Platform: | Size: 37888 | Author: | Hits:

[Software Engineering] Digital_Filter_implementation_by_FPGA

Description: 1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on fpgas 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in fpgas 7.视频图像处理与分析的网络资源
Platform: | Size: 1969152 | Author: carol | Hits:

[Software Engineering] medianfilter

Description: 基于vhdl图像处理中值滤波器，关于图像处理的好文章。-VHDL-based image processing median filter, a good deal about graphics article Ha ha
Platform: | Size: 249856 | Author: 张海风 | Hits:

[VHDL-FPGA-Verilog] MedFilter_VHDL

Description: 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.
Platform: | Size: 2048 | Author: mike.chen | Hits:

[VHDL-FPGA-Verilog] median_filterCode

Description: 采用快速中指滤波算法实现图像的中值滤波，使用VHDL语言ISE环境-Image Median Filter
Platform: | Size: 12288 | Author: 若谙 | Hits:

[Other] Appendix11

Description: Median Filter In Verilog
Platform: | Size: 222208 | Author: zerocool | Hits:

[Other] mul

Description: 加法器树乘法器结合了移位相加乘法器和查找表乘法器的优点。它使用的加法器数目等于操作数位数减 1 ，加法器精度为操作数位数的2倍，需要的与门数等于操作数的平方。 因此 8 位乘法器需要7个15位加法器和64个与门-Adder tree multiplier multiplier combination of shift and add multiplier advantage of look-up table. It uses the adder operand is equivalent to the median minus 1, adder operand median accuracy of the 2-fold, and the gate count required operand equal to the square. 8-bit multiplier, therefore the need for 7 and 15 adder 64 and the door
Platform: | Size: 1024 | Author: 肖毅 | Hits:

[VHDL-FPGA-Verilog] HG_chufaqi_clajiafaqi

Description: VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
Platform: | Size: 2048 | Author: Huanggeng | Hits:

[Software Engineering] median

Description: 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1, b1, c1)
Platform: | Size: 2048 | Author: 刘文英 | Hits:

[VHDL-FPGA-Verilog] MEDIAN.v

Description: fpga 的 median的verilog实现-median of verilog implementation
Platform: | Size: 1024 | Author: xyz | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

[VHDL-FPGA-Verilog] median-filter

Description: 基于FPGA的图像中值滤波算法的优化及实现vhdl-中值滤波 利用VHDL语言实现三级流水线中值滤波-FPGA-based image filtering algorithm optimization and realization of vhdl-median filter using VHDL language three pipelined median filter
Platform: | Size: 1024 | Author: 站长 | Hits:
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