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Description: 系统启动时检测内存状况的软件C代码，程度有点深，具备了C高级编程知识的朋友们可以参考研习。-Boot time memory status detection software C code, the degree of bit depth, with a high-level programming knowledge of C friends can refer to the study.
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Size: 144384 |
Author: Michael |
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Description: 超声波测距器
测距范围7CM-11M，堆栈在4FH以上，20H用于标志
显示缓冲单元在40H-43H，使用内存44H、45H、46H用于计算距离-Ultrasonic rangefinder rangefinder scope 7CM-11M, the stack in 4FH above, 20H for buffer unit showed signs in the 40H-43H, the use of memory 44H, 45H, 46H used to calculate the distance
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Size: 2048 |
Author: 思考 |
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Description: The Synthetic PIC
Verion 1.1
This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.
It is not, and is not intended as, a high fidelity circuit simulation.
This package includes the following files. Note that the license agreement
is stated in the main VHDL file, PICCPU.VHD and common questions are answered
in the file SYNTHPIC.TXT
Files:
README.TXT This file..
SYNTHPIC.TXT Questions and Answers
PICCPU.VHD Main processor VHDL file
PICALU.VHD ALU for the PICCPU
PICREGS.VHD Data memory
PICROM.VHD Program memory (created by HEX2VHDL utility)
PICTEST.VHD Simple test bench I used to do testing (optional)
PICTEST.CMD My Viewlogic ViewSim command file (again, optional)
TEST1.ASM First program I assembled and ran on it.
TEST2.ASM Another test program..
TEST3.ASM Yet another..
TEST4.ASM Yet another..
TEST5.ASM Yet another..
TEST6.ASM Yet another..
HEX2VHDL.CPP Utility for converting -The Synthetic PICVerion 1.1This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.It is not, and is not intended as, a high fidelity circuit simulation.This package includes the following files. Note that the license agreementis stated in the main VHDL file , PICCPU.VHD and common questions are answeredin the file SYNTHPIC.TXTFiles: README.TXT This file .. SYNTHPIC.TXT Questions and AnswersPICCPU.VHD Main processor VHDL filePICALU.VHD ALU for the PICCPUPICREGS.VHD Data memoryPICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it.TEST2.ASM Another test program. . TEST3.ASM Yet another .. TEST4.ASM Yet another .. TEST5.ASM Yet another .. TEST6.ASM Yet another .. HEX2VHDL.CPP Utility for converting
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Size: 48128 |
Author: likui |
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Description: c8051F060CAN通信测试程序,可写入某内存地址数据及读出.-c8051F060CAN communications test procedure, the data can be written to a memory address and read out.
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Size: 48128 |
Author: 黄标 |
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Description: Vs2003平台下写的，作测试用的代码，实现的包括内存泄漏检测，宏定义，指向指针的指针等相关测试-Vs2003 platform written the code for testing, implementation, including memory leak detection, macro, point to a pointer to other related test
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Size: 1502208 |
Author: 未愈书生 |
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Description: 本光盘包含的应用程序如下：
Test1 C语言编程
Test2 硬件测试
Test3 GPIO应用
Test4 定时器应用
Test5 ADC应用
Test6 SPI接口应用
SPI接口DAC(SPI_DAC5617)
SPI_DAC_ADC
SPI存储器扩展（SPI_EEPROM）
Test7 SCI应用
中断模式（SCI_interrupt）
状态查询模式（SCI_status）
Test8 CAN总线应用
CAN接收操作
CAN发送操作
Test9 Flash应用
-This CD contains the following applications: Test1 C language programming Test2 Test3 GPIO hardware test application Test4 timer application Test5 ADC application Test6 SPI interface applications SPI Interface DAC (SPI_DAC5617) SPI_DAC_ADC SPI memory expansion (SPI_EEPROM) Test7 SCI interrupt the application mode (SCI_interrupt) status query mode (SCI_status) Test8 CAN bus applications CAN receiver operating CAN transmit operation Test9 Flash Application
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Size: 2402304 |
Author: huojianteng |
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Description: 易语言内存运行，无需释放资源，直接内存加载运行-Easy language memory to run, no need to release resources, and direct memory load and run
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Size: 52224 |
Author: 周华健 |
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Description: 已知线性表（a1 a2 a3 …an）按顺序存于内存，每个元素都是整数，试设计用最少时间把所有值为负数的元素移到全部正数值元素前边的算法-Order known linear form (a1 a2 a3 ... an) stored in the memory, each element is an integer, with the least time trial design value is negative elements over all positive numerical elements front algorithm
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Size: 293888 |
Author: 邢雪 |
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Description: 1. RISC工作每执行一条指令需要八个时钟周期。RISC的复位和启动通过rst控制，rst高电平有效。Rst为低时，第一个fetch到达时CPU开始工作从Rom的000处开始读取指令，前三个周期用于读指令。
在对总线进行读取操作时，第3.5个周期处，存储器或端口地址就输出到地址总线上，第4--6个时钟周期，读信号rd有效，读取数据到总线，逻辑运算。第7个时钟周期，rd无效，第7.5个时钟地址输出PC地址，为下一个指令做好准备
对总线写操作时，在第3.5个时钟周期处，建立写的地址，第4个时钟周期输出数据，第5个时钟周期输出写信号。至第6个时钟结束，第7.5时钟地址输出PC地址，为下一个指令周期做好准备。
2. 操作过程：新建工程，编译compile all，然后仿真，在wave窗口加入要观察的信号，然后run –all，结束时完成test1的测试，重复两次run –all完成test2，test3的波形仿真。
-1. RISC work every eight clock cycles to execute an instruction needs. RISC reset and start by rst control, rst active high. Rst is low, the first CPUs fetch arrives starting from Rom s 000 start reading instruction, the first three cycles for reading instruction.
When the read operation is performed on the bus, at 3.5 cycles, memory, or port address output to the address bus, 4- 6 clock cycles, and the read signal rd, read data to the bus, a logic operation. 7 clock cycles, rd invalid, 7.5 PC clock address output address, ready for the next instruction
The write operation on the bus, in Section 3.5 of the clock cycle, to establish a write address, and four clock cycles and output data, the fifth clock cycle output write signal. To the end of the six clock the 7.5 clock address output PC address, ready for the next instruction cycle.
Operation: new construction, the compiler compile all, and simulation, join in the wave window to observe the signal, then the run-all completed by the
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Size: 1026048 |
Author: 宋颖 |
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Description: create timer and register it.Memory allocation and freeing are controlled by the regular library routines malloc() and free().
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Size: 3072 |
Author: vqzjpr |
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Description: stm32内存管理，支持智能指针和碎片整理，测试函数有 Test1 和 Test2-STM32 memory management, support for smart pointers and fragmentation, test functions are Test1 and Test2
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Size: 4581376 |
Author: 邹宜然 |
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Description: 两个多位十进制数相加，被加数均以 ASCII 码形式各自顺序存放在以
DATAl 和 DATA2 为首的 5 个内存单元中(低位在前)，结果送回 DATAl 处-More than two decimal addition, summand ASCII codes are stored in the respective order to DATAl and DATA2 led by five memory units (previous low), the results back at DATAl
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Size: 2048 |
Author: 关 |
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Description: 设计文法类，实现对文法G[S]=(Vt, Vn, P, S)的文件读写
文法的文件表示形式以及内存表示形式可自定义
文法就是3个集合+1个符号，重点（难点）就是产生式集合
产生式具有结构，可用于推导，是要特别注意的地方
如约定只读写产生式集合，一个示例如下（文件内容）：
S -> a
S -> aSb
也即首个非终结符S为开始符号，然后分析得到里面的终结符集={a, b}，非终结符集={S}，产生式集(略）。
文法的文本形式可根据自己需要自由定义
例如，直接自己给出3个集合。
(Design grammar class, to achieve grammar G [S] = (Vt, Vn, P, S) of document literacy grammar file representation and memory representation can be customized grammar is three set+1 symbols Key (difficulty) is a collection of production with a production structure, can be used to derive, is paying particular attention to areas such as reading and writing production agreement only set an example as follows (file contents): S-> a S-> aSb That is the first non-end symbol S is the start symbol, and then get inside the terminator analysis set = {a, b}, nonterminals set = {S}, production sets (omitted). Text grammar can be freely defined according to their needs, for example, direct yourself to give three sets.)
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Size: 1024 |
Author: 陈桐 |
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