Search - memory verilog

[Other resource] NAND256R3A_VE1

Description: 256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual -256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
Platform: | Size: 203769 | Author: 陈强 | Hits:

[Other resource] rom

Description: Read-only memory,Verilog code
Platform: | Size: 8237 | Author: leigh lee | Hits:

[SDK] Samsung 8G x 8 Bit NAND Flash Memory SPEC & Simulatiom model

Description: Samsung 8G x 8 Bit NAND Flash Memory SPEC and verilog Simulatiom model
Platform: | Size: 1328527 | Author: asd12321 | Hits:

[CSharp] OS课题设计

Description: 任务设计一个虚拟存储区和内存工作区，并使用下述算法计算访问命中率。（1）先进先出的算法（FIFO）（2）最近最少使用算法（LRU）（3）最佳淘汰算法（OPT）（4）最少访问页面算法（LFU）（5）最近最不经常使用算法（NUR）命中率=（1 – 页面失效次数）/页地址流长度-mission design a virtual memory storage area and the work area and to use the following algorithm to visit the hit rate. (1) FIFO algorithm (FIFO) (2) at least recently used algorithm (LRU) (3) eliminated the best algorithm (OPT) (4) at least visit pages algorithm (LFU) (5) most recently used algorithm (NUR) life China rate = (1-pages failure number)/page-length addre
Platform: | Size: 2048 | Author: 东方少秋 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[VHDL-FPGA-Verilog] VHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] memoryverilog

Description: 一个关于MEMORY设计的原代码,使用VERILOG编写的希望对大家有些帮助-one of the original Memory design code prepared by the use of verilog we hope to help some
Platform: | Size: 26624 | Author: 王平 | Hits:

[VHDL-FPGA-Verilog] NAND256R3A_VE1

Description: 256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual -256Mbits (x8) 528 Bytes Page, NAND Flash Memory Verilog HDL Model User Manual
Platform: | Size: 203776 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] ram

Description: RAM， Random-access memory，Verilog code-RAM, Random-access memory, Verilog code
Platform: | Size: 14336 | Author: leigh lee | Hits:

[VHDL-FPGA-Verilog] rom

Description: Read-only memory,Verilog code
Platform: | Size: 8192 | Author: leigh lee | Hits:

[VHDL-FPGA-Verilog] Content_Addressable_Memory

Description: Content Addressable Memory 的verilog源代码。经过modelsim仿真。-Content Addressable Memory of Verilog source code. After ModelSim simulation.
Platform: | Size: 1024 | Author: lianlianmao | Hits:

[VHDL-FPGA-Verilog] memory

Description: Verilog写的内存控制器代码. 很好,很容易看懂-Verilog code to write the memory controller
Platform: | Size: 2048 | Author: www | Hits:

[VHDL-FPGA-Verilog] RAM_Examples

Description: Verilog hdl code for representing ram and rom "memory" using many methods
Platform: | Size: 5120 | Author: Muftah | Hits:

[Other] Memory

Description: Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
Platform: | Size: 846848 | Author: Lokous | Hits:

[OS Develop] RT_8051_memory

Description: 8051 RT Memory Verilog-8051 Memory
Platform: | Size: 4096 | Author: feisikair | Hits:

[VHDL-FPGA-Verilog] dpmem2clk.tar

Description: Dual port memory VHDL/Verilog design
Platform: | Size: 3072 | Author: Ravi | Hits:

[VHDL-FPGA-Verilog] MEMORY_CONTROLLER_ASSIGNMENT

Description: memory controller design in verilog
Platform: | Size: 1593344 | Author: arun | Hits:

[VHDL-FPGA-Verilog] Verilog秒表设计

Description: 用verilog在basys2开发板上实现一个具有置零、开始、暂停、记忆功能的秒表。(Implement a stopwatch which containing reset,pause,start,memory functions with the verilog on the vivado based on the basys2 development board.)
Platform: | Size: 637952 | Author: terriao | Hits:

[VHDL-FPGA-Verilog] memory生成和接口说明

Description: memory生成结构说明文档；使用Verilog语言(Memory generated structure description document)
Platform: | Size: 356352 | Author: zhaolinWang | Hits:

[VHDL-FPGA-Verilog] Memory Verilog

Description: ROM,RAM (dual port)- Verilog
Platform: | Size: 1585 | Author: gsrwork2017@gmail.com | Hits:

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