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[Other] platform_fpga_design_high-performance_dsp

Description: full design for the 2x2 MIMO on FPGA, very amazing pdf to give the design for the block of the 2x2 mimo using the alamouti coding.
Platform: | Size: 967680 | Author: Xan | Hits:

[Post-TeleCom sofeware systems] mimo_dectection

Description: mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过-mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on
Platform: | Size: 2194432 | Author: | Hits:

[VHDL-FPGA-Verilog] MIMO

Description: 介绍MINO系统在FPGA下如何开发，详细的介绍了过程！-MINO system introduced in the FPGA how to develop a detailed introduction to the process!
Platform: | Size: 10748928 | Author: lijiaxu | Hits:

[VHDL-FPGA-Verilog] Channel_EstimationMIMO

Description: 本文对MIMO技术中的信道估计、空时编码和单载波频域均衡技术（SC-FDE）及其在FPGA上的实现进行了深入的研究-In this paper, MIMO channel estimation techniques, space-time coding and single-carrier frequency domain equalization (SC-FDE) and its implementation on FPGA-depth study carried out
Platform: | Size: 1149952 | Author: w | Hits:

[VHDL-FPGA-Verilog] FPGA-Implementation-for-MIMO-ofdm

Description: FPGA implementation of KBEST algorithm for MIMO OFDM system. -FPGA implementation of KBEST algorithm for MIMO OFDM system
Platform: | Size: 463872 | Author: wzx | Hits:

[Post-TeleCom sofeware systems] QR

Description: QR分解是球形MIMO检测算法必不可少的环节,本代码采用m语言描述了QR分解分解具体怎么实现,而不是直接调用matlab内部函数,采用的是QR分解的脉动阵列结构,据此代码可轻易实现QR分解的FPGA设计-QR decomposition is an essential part of the spherical MIMO detection algorithm, the code uses QR decomposition decomposition m language to describe specifically how to achieve, rather than a direct call matlab internal function, using the QR decomposition systolic array structure, pursuant to which the code can be easily QR decomposition FPGA design
Platform: | Size: 3072 | Author: logic | Hits:

[assembly language] simple-mimo-encoder

Description: fpga niosII assembly language code for mimo encoders
Platform: | Size: 1024 | Author: anis370 | Hits:

[Software Engineering] 4954-421

Description: FPGA implementation of DDC for SDR and MIMO Applications
Platform: | Size: 163840 | Author: kishore | Hits:

[VHDL-FPGA-Verilog] mimo_dectection20160112

Description: mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过-mimo detection algorithms on FPGA, including a minimum zero forcing detection algorithm and ML detection algorithm has been through in the ISE simulation
Platform: | Size: 1784832 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] qam16 modulator

Description: QAM16 MODULATOR VERILOG CODE ON FPGA
Platform: | Size: 1024 | Author: GIRISH | Hits:

[Other] rapport 9

Description: Implementing a real-time MIMO-OFDM physical layer over FPGA
Platform: | Size: 5277696 | Author: kaissoun | Hits:

[Other] rad-wpc-fbmc

Description: FBMC transmitter offers low power and high speed than the OFDM transmitter.Spectral efficiency is high. sidelobe problem is eliminated by using filter bank.
Platform: | Size: 418816 | Author: paramu | Hits:

[Other] Comparative study of FFA architectures using different multiplier and adder topologies

Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Platform: | Size: 1123027 | Author: nalevihtkas | Hits:

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