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[Other resource] Digital-Design-and-Computer-Architecture-verilog.r

Description: 《数字设计和计算机体系结构》一书MIPS verilog源码。
Platform: | Size: 3473 | Author: guo | Hits:

[VHDL-FPGA-Verilog] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5120 | Author: 刘陆陆 | Hits:

[ARM-PowerPC-ColdFire-MIPS] signal_cpu_sort

Description: Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
Platform: | Size: 8192 | Author: 張大小 | Hits:

[Other] arm7-verilog

Description: 这是arm7处理器的verilog全代码，仔细研究一下，会对CPU和verilog均有很大的裨益。-This is ARM7 processor Verilog-wide code carefully, CPU and Verilog will have great benefits.
Platform: | Size: 37888 | Author: 王云 | Hits:

[VHDL-FPGA-Verilog] mipsinverilogandvhdl

Description: mips prcessor in Verilog and vhdl-mips prcessor in vhdl and Verilog
Platform: | Size: 7168 | Author: 张六封 | Hits:

[ARM-PowerPC-ColdFire-MIPS] verilog

Description: 8bit alu use verilog hdl
Platform: | Size: 8192 | Author: 周微微 | Hits:

[MPI] controller

Description: MIPS处理器的控制verilog代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS control processor Verilog code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Digital-Design-and-Computer-Architecture-verilog.r

Description: 《数字设计和计算机体系结构》一书MIPS verilog源码。
Platform: | Size: 3072 | Author: guo | Hits:

[VHDL-FPGA-Verilog] MIPS

Description: 组成原理大作业--基于MIPS的运算器设计，内附详细设计文档，包含设计文档和使用手册，主程序，测试程序，还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条，用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and user manual, the main program, testing procedures, as well as the design of the diagram and so on. Can be implemented to achieve a basic computing device on the MIPS instruction were related to 17, prepared using Verilog.
Platform: | Size: 3060736 | Author: da | Hits:

[VHDL-FPGA-Verilog] mipsCPU

Description: MIPS CPU tested in Icarus Verilog
Platform: | Size: 20480 | Author: imromeo | Hits:

[Other] ask10

Description: This a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.-This is a simple MIPS processor datapath written in VERILOG hardware language. You can see the signals when emulating in signalscan. Compile it with verilog in linux.
Platform: | Size: 2048 | Author: thesky | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPS

Description: 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Platform: | Size: 17408 | Author: 张鹤 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_multi

Description: mips processor multicycle non-pipelined microprocessor by verilog
Platform: | Size: 9216 | Author: JACD | Hits:

[VHDL-FPGA-Verilog] mips

Description: 使用verilog設計的MIPS處理器，mips處理機的模擬且可合成驗証-MIPS processor using the verilog design, mips processor synthesis of analog and can be verified
Platform: | Size: 4096 | Author: 張日 | Hits:

[assembly language] hmc-mips-7-3-15

Description: mips processor in verilog
Platform: | Size: 1691648 | Author: henry | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] multi-cycle-MIPS

Description: multicycle-MIPS verilog implementation
Platform: | Size: 3072 | Author: ramtin | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] mips

Description: mips verilog进行编写cpu,其中包括了若干的基本指令(use the verilog language to programme the CPU)
Platform: | Size: 4096 | Author: 光亮 | Hits:

[Other] MIPS-Verilog-master

Description: MIPS R3000 microprocessor core
Platform: | Size: 183296 | Author: sdkjjb | Hits:
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