Search - mod counter

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Description: with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,electronic voting machine,mod 16 counter,jk flip flop.please accept these codes and make me member of this site.so that i can download code from this site also.i really needed codes please accept that as soon as possible.
Platform: | Size: 2048 | Author: nitin | Hits:

[Other] cnt8

Description: 用JK-flip-flop做的8进制counter-mod-8-counter
Platform: | Size: 385024 | Author: suhang | Hits:

[VHDL-FPGA-Verilog] counter_advanced

Description: A counter that starts from 0 and increments mod 16 on each rising edge of the clock
Platform: | Size: 1024 | Author: Ahmed | Hits:

[VHDL-FPGA-Verilog] mod10asynchro

Description: this is a verilog code for asynchronous mod-10 counter.its also called a decade counter.
Platform: | Size: 23552 | Author: swapna | Hits:

[VHDL-FPGA-Verilog] mod6asynchro

Description: this is a code for mod-6 asynchronous counter in verilog.
Platform: | Size: 24576 | Author: swapna | Hits:

[Windows Develop] shiziluoji

Description: 三位二进制加1与加2计数器：三位二进制模5计数器。当外部输入X = 1时，计数器加2计数；外部输入X = 0时，计数器加1计数。“模5”为逢“5”进1计数。原始条件：使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 )，设计三位二进制模5计数器。 -The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X = 1 when the external input, the counter plus 2 counts external input X = 0, the counter by 1 count. " Die 5" for every " 5" into a count. Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
Platform: | Size: 201728 | Author: 王军 | Hits:

[VHDL-FPGA-Verilog] counter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

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[Other] vhdlcodes

[Other] cnt8

[VHDL-FPGA-Verilog] counter_advanced

[VHDL-FPGA-Verilog] mod10asynchro

[VHDL-FPGA-Verilog] mod6asynchro

[Windows Develop] shiziluoji

[VHDL-FPGA-Verilog] counter

[VHDL-FPGA-Verilog] mod_6counter

[VHDL-FPGA-Verilog] 04301090a-u-law

[Software Engineering] New-folder

[Game Engine] MetahookEngine0.2

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