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Description: 用JK-flip-flop做的8进制counter-mod-8-counter
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Size: 385024 |
Author: suhang |
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Description: this is a code for mod-6 asynchronous counter in verilog.
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Size: 24576 |
Author: swapna |
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Description: 三位二进制加1与加2计数器 ：三位二进制模5计数器。当外部输入X = 1时，计数器加2计数；外部输入X = 0时，计数器加1计数。“模5”为逢“5”进1计数。
原始条件：使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 )，设计三位二进制模5计数器。
-The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X = 1 when the external input, the counter plus 2 counts external input X = 0, the counter by 1 count. " Die 5" for every " 5" into a count. Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
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Size: 201728 |
Author: 王军 |
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Description: its a mod 6 counter designed using structural modelling
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Size: 2048 |
Author: chhavi |
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Description: This a source for counter-strike 1.6. We can make mod like CSO with this code.
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Size: 110592 |
Author: Taraf |
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