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[VHDL-FPGA-Verilog] mc8051_cyclone_nios

Description: 增强型8051的VHDL源代码，两个周期执行一条指令，仿真工具为Modelsim，开发板为Altera的EP1C20开发板-enhanced 8051 VHDL source code, the implementation of a two-cycle instruction, simulation tools for Modelsim, development board for the Altera EP1C20 development board
Platform: | Size: 2000896 | Author: 柳如飞 | Hits:

[uCOS] foreignsp

Description: fli接口程序，实现接口MODELSIM 与PCI之间的互访-fli interface program to achieve MODELSIM PCI interface between the visits
Platform: | Size: 2048 | Author: 江涛 | Hits:

[Other] activehdl6.2的crack

Description: activehdl的 crack，高手破解 ，很多人用过 绝对好用，如有需要者可以下载使用-activehdl the crack, crack experts, many people used the absolute ease of use, and if necessary can be used to download
Platform: | Size: 63488 | Author: dsfd | Hits:

[Other] Keygen

Description: modelsim破解工具 安装modelsim后运行它即可破解-modelsim crackers after installation modelsim run it can break
Platform: | Size: 228352 | Author: 苏醒 | Hits:

[VHDL-FPGA-Verilog] ModelSim.SE.v6.0a_keygen

Description: ModelSim分析设计教程\ModelSim.SE.v6.0许可生成器，生成license文件-ModelSim Analysis and Design Guide \ ModelSim.SE.v6.0 permission generator , document generation license
Platform: | Size: 220160 | Author: 袁汇 | Hits:

[VHDL-FPGA-Verilog] RISCMCU

Description: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Platform: | Size: 594944 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] ModelSim.SE.v6.2bcrack

Description: 如题，ModelSim se 6.2的破解方法说明，pdf版本，很好用。-Such as title, ModelSim se 6.2 description of the crack, pdf version, it just works.
Platform: | Size: 52224 | Author: ln | Hits:

[VHDL-FPGA-Verilog] uart2fli

Description: Modelsim FLI接口设计实例，适合学习Modelsim fli接口编程者学习。-Modelsim FLI interface design for learning Modelsim fli learn programming interface.
Platform: | Size: 92160 | Author: xxx | Hits:

[OS program] vh2sc

Description: 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and booleans this in order to maximise performance. The aim of the converter is to produce a cycle accurate model of synthesisable VHDL code. The converter runs on Windows Example1: Simple counter Convert the counter.vhd file to SystemC, c:VHDL2SystemCexample1>vh2sc-v-mti count.vhd VH2SC-> VHDL to SystemC Converter Ver 0.21** Alpha Release** (c)HT-Lab 2007 SQLite Version : 3.3.13 Parsing File : count.vhd Line 9** Info : library ieee ignored Line 28** Info : VH2SC Translation Disabled Line 32** Info : VH2SC Translation Re-Enabled Line 37** Info : process() translated to process_line37 Writing Header File : cnt.h Writing C++ File : cnt.cpp ** Info : Modelsim SC_MODULE_EXPORT(cnt) macro added The-v is a verbose flag and-mti is requi
Platform: | Size: 819200 | Author: whiz | Hits:

[Crack Hack] ModelSim.SE.v6.0-ROR.ZIP

Description: modelsim crack versin 6
Platform: | Size: 220160 | Author: islam | Hits:

[Linux-Unix] pli_socket_example_unix

Description: unix下C程序和modelsim中的verilog程序进行socket通信的实例代码及说明，非常实用-example code and notes of socket communication between c under unix and verilog under modelsim, it is very useful
Platform: | Size: 22528 | Author: 孙磊 | Hits:

[Embeded-SCM Develop] 13

Description: Cadence的ncsc的例子。 ------------------------ vcd2wlf.bat:将VCD文件转换为modelsim波形格式的批处理。 vc.bat:VC命令行编译的批处理。需要针对自己机器的路径做一下修改。一般我们用VC的集成环境，但如果你习惯用命令行，可以用这个。 -Cadence' s ncsc example.------------------------ Vcd2wlf.bat: the VCD format files into batch modelsim waveform. vc.bat: VC command-line compiler batch. The need for their own path of the machine to do something changes. In general we use the VC integrated environment, but if you are accustomed to the command line, you can use this.
Platform: | Size: 2048 | Author: zidane | Hits:

[VHDL-FPGA-Verilog] keygen

Description: modelsim se 6.2b版本的keygen.exe-modelsim se 6.2b keygen.exe
Platform: | Size: 186368 | Author: 黄生 | Hits:

[VHDL-FPGA-Verilog] eetop.cn_Crack_Modelsim.SE.6.6

Description: Modelsim 6.6c keygen
Platform: | Size: 667648 | Author: 王京 | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[Other] 08638294RS232

Description: modelsim 安装与破解-modelsim anzhuangyupojie
Platform: | Size: 3072 | Author: yuexinqi | Hits:

[VHDL-FPGA-Verilog] ModelSim-Altera61g_CRACK

Description: modelsim 6.2破解,对于ALTERA 器件-MODELSIM 6.2 CRAK FOR ALTORAL CHIP
Platform: | Size: 308224 | Author: wangfei | Hits:

[CSharp] hex2bin

Description: 一个关于h.264视频解码的简单的C语言程序，可将modelsim仿真输出的*.log文件转换成*.yuv格式-A simple C language programabout h.264 video decoding :convert text format to binary .264
Platform: | Size: 1024 | Author: huanghong | Hits:

[VHDL-FPGA-Verilog] code

Description: c++语言转verilog语言，程序员不需要学习verilog即可对fpga原型进行快速仿真，本例为catapult c语言的fft程序，可以利用catapult转换工具转成verilog语言， 用modelsim进行仿真，并且可以加各种约束。-c++ program translate verilog program。
Platform: | Size: 17408 | Author: wangjun | Hits:

[VHDL-FPGA-Verilog] cbf

Description: catapult c 常规波束形成程序，已转化为verilog语言，并且完成modelsim验证-catapult c beamforming program
Platform: | Size: 3072 | Author: wangjun | Hits:
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