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[Other Embeded program] 发一个基于ModelSim仿真的Verilog源代码包

Description: 发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
Platform: | Size: 74752 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] rtl

Description: 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
Platform: | Size: 93184 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] QPSK2154

Description: QPSK的VERLOG源码，在MODELSIM下的一个工程，有测试向量。-QPSK VERLOG source of the MODELSIM of a project, test vector.
Platform: | Size: 23552 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] crc3321

Description: CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
Platform: | Size: 26624 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] hdb3_verilog

Description: modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
Platform: | Size: 22528 | Author: chengroc | Hits:

[VHDL-FPGA-Verilog] Modelsim_fredevider_testbench_TEXTIO

Description: 此文档通过分频器的例子描述了如何使用modelsim，如何编写testbench以及textio的使用-This document is an example through the divider describes how to use the modelsim, how to write a testbench and use textio
Platform: | Size: 256000 | Author: 二米阳光 | Hits:

[VHDL-FPGA-Verilog] dds

Description: verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
Platform: | Size: 2594816 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

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