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[VHDL-FPGA-Verilog] sim

Description: 通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真-Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
Platform: | Size: 33792 | Author: 来来 | Hits:

[VHDL-FPGA-Verilog] decoder35

Description: decoder verilog. it is a 3 t0 5 decoder that compile with modelsim.
Platform: | Size: 1024 | Author: MohammadReza | Hits:

[VHDL-FPGA-Verilog] decoder

Description: 3_8译码器 verilog代码 modelsim仿真-3_8 verilog code in modelsim simulation decoder
Platform: | Size: 1024 | Author: zhou | Hits:

[VHDL-FPGA-Verilog] Behavioral-Modeling

Description: A Code that illustrates 12 bit switch, 2x1 Mux, 2x4 Decoder in behavioral modeling in Verilog HDL using modelsim IDE
Platform: | Size: 1024 | Author: Asad Abbas | Hits:

[VHDL-FPGA-Verilog] decoder

Description: 对于通信传输中常用的曼彻斯特编码给出了详细的Verilog程序，程序在Modelsim中调试通过。-For the transmission of commonly used Manchester coding are also given Verilog process, the process of debugging in Modelsim through.
Platform: | Size: 1024 | Author: LT | Hits:

[VHDL-FPGA-Verilog] 38-decoder

Description: 3-8译码器的Verilog硬件语言实现，开发环境是ModelSim-The 3-8 decoder Verilog hardware language development environment is ModelSim
Platform: | Size: 3072 | Author: klxl | Hits:

[VHDL-FPGA-Verilog] manchester_encoder

Description: 曼切斯特码解码器verilog程序，已通过ModelSIM仿真，可用-Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available
Platform: | Size: 1024 | Author: 王明明 | Hits:

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