Search - mult - CodeBus

Search - mult - List

[Windows Develop] 200521511239637 DL : 0: 这是一个收集整理网址的小东东GetLink，主要运用ini文件保存网址类别，dat文件保存网址，支持多视通信，可以直接从IE页面上拖放网址。 -this is a little tool name of GetLink that is used to collect website,It is used to save web s catalog by .ini file and to save website by .dat file and to insist mult-visual comunication and to draw website inderectly from IE browser
Update : 2008-10-13 Size : 113.09kb Publisher : 风风
[xml-soap-webservice] servlet_album10g DL : 0: servlet with intermedia about oracle multimedia -servlet with intermedia about oracle mult IMEDIA
Update : 2008-10-13 Size : 11.5kb Publisher : zhang
[Other resource] chapter1-2 DL : 0: 这是我学习《MATLAB程序设计与应用》刘卫国、陈昭平　一书时第一章和第二章的课后习题目录 exponential_e.m exsub.m fheritage.m initialise.m matrix.m matrix2.m matrixm.m matrix_c.m matrix_mul.m mult.m mywork1201.dll mywork1201.m normcdf_.m p41_4.m p41_5.asv p41_5.m p41_6.m p41_7.m p41_8.m p64_1.m p64_2.m p64_3.m p64_4.m p64_5.m p65_10_1.m p65_10_2.m p65_10_3.m p65_6.m p65_8.m-This is my learning "MATLAB design and application procedures," Liu Weiguo, Chenzhaobeng a first book chapters I and II of the after-school catalog exponential_e.m exsu Exercises b.m fheritage.m initialise.m matrix.m matrix 2.m matrixm.m matrix_c.m matrix_mul.m mult.m mywork1201.dll mywork1201.m normcdf_.m p41_ 4.m p41_5.asv p41_5.m p41_6.m p41_7.m p41_8.m p64_1.m p64_2.m p64_3.m p64_4.m p64_5.m p65_1 0_1.m p65_10_2.m p65_10_3.m p65_6.m p65_8.m
Update : 2008-10-13 Size : 13.55kb Publisher : 赵亮
[Multimedia program] live.2006.12.08.tar DL : 1: This code forms a set of C++ libraries for multimedia streaming, using open standard protocols (RTP/RTCP, RTSP, SIP).-This code forms a set of C libraries for mult imedia streaming. using open standard protocols (RTP / RTCP, RTSP, SIP).
Update : 2008-10-13 Size : 414.98kb Publisher : 张金沙
[Other resource] multi4 DL : 0: fulladder.vhd 一位全加器 adder.vhd 四位全加器 multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
Update : 2008-10-13 Size : 1.48kb Publisher : 杨奎元
[midi program] midiio DL : 0: 控制MIDI输入输出的程序。 View MIDI input messages in raw form or with text descriptions. Send MIDI messages using the mouse or from dialog controls. Select MIDI input and output devices from the application. Run multiple instances to demonstrate MIDI device sharing between applications.-MIDI input and output control procedures. View MIDI input messages in raw form or with text descriptions. Send MIDI messages using the mou se or from dialog controls. Select an MIDI input d output devices from the application. Run mult Attached instances to demonstrate MIDI device shar ing between applications.
Update : 2008-10-13 Size : 28.03kb Publisher : lixiao
[CSharp] CodeLab DL : 0: This is a command-line utility that runs through several benchmarks that exercise various aspects of Paint.NET. Every benchmark is multithreaded, and takes advantage of multiprocessor or multicore systems. -This is a command-line utility that runs th rough several benchmarks that exercise variou 's aspects of Paint.NET. Every benchmark is mult ithreaded. and takes advantage of multiprocessor or multi core systems.
Update : 2008-10-13 Size : 13.82kb Publisher : limaobing
[VHDL-FPGA-Verilog] Mult DL : 0: 这是我自己写的两个8位二进制数的乘法程序，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote two eight binary number multiplication procedure, In xilinx Spartan3E debugging has been successful, with the show to share with you!
Update : 2025-02-19 Size : 177kb Publisher : 许的开
[VHDL-FPGA-Verilog] mult DL : 0: 移位乘法器的输入为两个4位操作数a和b，启动乘法器由stb控制，clk信号提供系统定时。乘法器的结果为8位信号result,乘法结束后置信号done为1. 乘法算法采用原码移位乘法，即对两个操作数进行逐位的移位相加，迭代4次后输出结果。具体算法： 1. 被乘数和乘数的高位补0，扩展成8位。 2. 乘法依次向右移位，并检查其最低位，如果为1，则将被乘数和部分和相加，然后将被乘数向左移位；如果为0，则仅仅将被乘数向左移位。移位时，被乘数的低端和乘数的高端均移入0. 3. 当乘数变成全0后，乘法结束。 -err
Update : 2025-02-19 Size : 127kb Publisher : 良芯
[VHDL-FPGA-Verilog] mult DL : 0: 64位乘法器源码verilog,经过验证测试-64-bit multiplier source verilog, validated test
Update : 2025-02-19 Size : 59kb Publisher : zhang chi
[VHDL-FPGA-Verilog] MULT DL : 0: 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
Update : 2025-02-19 Size : 108kb Publisher : 韩思贤
[Embeded-SCM Develop] mult-switch DL : 0: AT89S51单片机的P1.0－P1.3接四个发光二极管L1－L4，P1.4－P1.7接了四个开关K1－K4，编程将开关的状态反映到发光二极管上。（开关闭合，对应的灯亮，开关断开，对应的灯灭）-AT89S51 MCU P1.0-P1.3 next four light-emitting diodes L1-L4, P1.4-P1.7 next four switches K1-K4, programming will reflect the status of switches on the light-emitting diodes. (Switch closed, the corresponding lights, switch off, the corresponding lights out)
Update : 2025-02-19 Size : 6kb Publisher : yusong
[VHDL-FPGA-Verilog] mult DL : 0: 这是一个mult源文件，用verilog语言写的，经过仿真正确。-This is a mult programm.
Update : 2025-02-19 Size : 4kb Publisher : yuedongxu
[VHDL-FPGA-Verilog] mult DL : 0: 用硬件语言VHDL进行编写乘法器，经过仿真，结果正确-VHDL language used to write hardware multiplier, through the simulation result is correct
Update : 2025-02-19 Size : 181kb Publisher : 王岩嵩
[MPI] mult DL : 0: Perfectly works parallel mult matrix programm on MPI
Update : 2025-02-19 Size : 2kb Publisher : Rufina
[VHDL-FPGA-Verilog] mult DL : 0: 16位乘法器,输入16位乘数，输出32位积，采用循环移位算法-a multplier
Update : 2025-02-19 Size : 1.07mb Publisher : Paul
[VHDL-FPGA-Verilog] Designs DL : 0: design files in verilog, alu, array mult, carry shift etc.
Update : 2025-02-19 Size : 37kb Publisher : p2p_123
[VHDL-FPGA-Verilog] complex_mult DL : 0: Complex mult in vhdl
Update : 2025-02-19 Size : 1kb Publisher : Yousri
[VHDL-FPGA-Verilog] quartus-mult DL : 0: mult,在quartusII中，以模块输入形式，仿真乘法器mult，得到时序图和功能图-a simulation example of mult
Update : 2025-02-19 Size : 292kb Publisher : beginner
[matlab] Mult&T DL : 0: Mult&T multivariable system
Update : 2025-02-19 Size : 736kb Publisher : doremamii

« 12 3 4 5 6 7 8 9 10 »