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[Books] fpga时钟设计 DL : 0: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将导致错误的行为，并且调试困难、花销很大。在设计PLD/FPGA时通常采用几种时钟类型。时钟可分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
Update : 2025-02-17 Size : 393kb Publisher : 与言
[SCM] data-shuzizhong DL : 0: 此文件是本人设计的一个多功能数字钟的详细资料,现供大家参考.-I designed a multi-function digital clock detailed information is available for your reference.
Update : 2025-02-17 Size : 25kb Publisher : 周
[Software Engineering] clock DL : 0: 大型设计中FPGA的多时钟设计策略，使用atmel-FPGA design of large-scale multi-clock design strategy, the use of Atmel
Update : 2025-02-17 Size : 252kb Publisher : 郭巍
[Process-Thread] clock DL : 0: 使用JAVA多线程编程技术编辑的时钟显示小软件-Multi-threaded programming using the JAVA technology editor clock showed small software
Update : 2025-02-17 Size : 11kb Publisher : 陈荣山
[VHDL-FPGA-Verilog] CLOCK DL : 0: 基于FPGA的多功能电子时钟的设计很经典的哦-FPGA-based multi-functional electronic clock designs are very classic Oh
Update : 2025-02-17 Size : 425kb Publisher : xhb
[SCM] clock DL : 0: 多功能电子钟、Proteus、源代码、原理图-Multi-functional electronic bell, Proteus, source code, schematics
Update : 2025-02-17 Size : 239kb Publisher : 碎骨
[assembly language] clock DL : 0: 很好的多功能数字钟的HDL代码不可多得的哦-Good multi-function digital clock of the HDL code rare Oh
Update : 2025-02-17 Size : 124kb Publisher : 张俊
[SCM] clock DL : 0: 资料中包括了利用凌阳61板和液晶块搭建一个多功能数字电子钟的源码和完整的电路原理图，理论上只要按照指示做，把程序烧进去，就能马上运行。是我一个完整的毕业设计。-Information, including the use of Sunplus 61 boards and blocks to build a multi-function LCD digital clock source and a complete circuit schematic diagram, in theory, as long as in accordance with the instructions, so that burned into the procedure can be run immediately. I graduated from a complete design.
Update : 2025-02-17 Size : 180kb Publisher : 曾明
[Other systems] clock DL : 0: 多功能电子时钟，具有时间显示，时间调整等功能。-Multi-function electronic clocks, time display, time adjustment functions.
Update : 2025-02-17 Size : 2kb Publisher : xuejing
[Other] CLOCK DL : 0: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Update : 2025-02-17 Size : 178kb Publisher : 张保平
[Process-Thread] clock DL : 0: 使用systemC模擬多重現成-SystemC simulation of multi-use off-the-shelf
Update : 2025-02-17 Size : 2.41mb Publisher : 蔡勝凡
[VHDL-FPGA-Verilog] clock DL : 0: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
Update : 2025-02-17 Size : 1kb Publisher : 许毅民
[Embeded-SCM Develop] Clock DL : 0: 实现多功能时钟，能设定时间，与设置闹铃时间。使用89C52单片机+DS1302时钟芯片+DS7279解码芯片+数码管LCD显示-Achieve multi-functional clock, can set the time, and set the alarm time. 89C52 single-chip microcomputer use+ DS1302 clock chip decoder chip++ DS7279 digital LCD display control
Update : 2025-02-17 Size : 19kb Publisher : 陈双喜
[assembly language] complex-digital-clock DL : 0: 一个多功能数字钟汇编程序，具有基本时钟功能，年月日，秒表，24小时的倒计时，闹钟五个功能。-A multi-functional digital clock assembler with the basic clock function, date, stopwatch, 24-hour countdown, the five functional alarm clock.
Update : 2025-02-17 Size : 2kb Publisher : wei
[Other] E.arlarm.clock DL : 0: 能显示年月日，切能设置定时闹钟的多功能电子钟-Showing the date, cut from time to time to set up multi-function alarm clock Electronics
Update : 2025-02-17 Size : 1.79mb Publisher : 郑晨
[GUI Develop] MULTI-FUNCTION-TIMER DL : 0: 利用Visual Basic编写的多功能计时器，能做秒表，也能做时钟。-The use of Visual Basic preparation of multi-functional timer, stopwatch can also do clock.
Update : 2025-02-17 Size : 21kb Publisher : 陈玲
[VHDL-FPGA-Verilog] 2 DL : 0: FPGA设计中几个基本问题的分析及解决多时钟系统，时钟设计，时钟歪斜，门控时钟，毛刺信号及其消除，FPGA中的延时设计，FPGA设计应注意的其它问题-FPGA design analysis of a few basic questions and solve multi-clock system, clock design, clock skew, clock gating, and the elimination of burr signal, FPGA design of the delay, FPGA design should pay attention to other issues
Update : 2025-02-17 Size : 47kb Publisher : 江凯
[VHDL-FPGA-Verilog] clock DL : 0: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Update : 2025-02-17 Size : 2.96mb Publisher : 陈涵
[VHDL-FPGA-Verilog] clock DL : 0: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Update : 2025-02-17 Size : 961kb Publisher : Stone Lei
[VHDL-FPGA-Verilog] multi-clock-design DL : 0: FPGA 多时钟系统设计的简介。文章介绍了多种多时钟的设计的方案。-FPGA introduction to multi-clock system design. This paper introduces the design of a variety of multi-clock scheme.
Update : 2025-02-17 Size : 824kb Publisher : 王龙

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