Search - multi stage CIC

Search - multi stage CIC - List

[Software Engineering] jifenlvboqi DL : 0: 为了解决软件无线电通信系统中频采样之后的极大数据量在基带处理部分对DSP计算的压力,常采用多速率处理技术.多速率处理过程中需要使用积分梳状滤波器、半带滤波器和高阶FIR滤波器.在分析了积分梳状滤波器的结构和特性的基础上,阐述了多级CIC滤波器一种高效的FPGA实现方法,该方法的正确性和可行性通过Quartus Ⅱ的时序仿真分析得以验证,实际中可以推广应用.-In order to solve software-defined radio communications system after IF sampling of great amount of data to the DSP in the baseband processor part of the calculation of the pressure, often using multi-rate processing technology. Multi-rate processing need to use the integrator comb filter, half-band filters and high-order FIR filter. in the analysis of the integrator comb filter structure and characteristics, based on the multi-stage CIC filter described an efficient FPGA implementations, the correctness and feasibility of the method adopted by the timing Quartus Ⅱ simulation analysis can be verified in practice can be applied.
Update : 2025-04-26 Size : 176kb Publisher : 王楚宏
[DSP program] CIC-filter-design DL : 0: CIC滤波器的设计，实验中用到的所有完整的工程文件在test5文件夹下。（1）一级CIC滤波器的设计，完整的工程文件包含： cic_only.mdl ma_only_standard.mdl （2）多级CIC滤波器的设计，完整的工程文件包含： cic_5th_order_pipe1.mdl cic_5th_order_pipe2.mdl fixed_point_cic.mdl （3）CIC插值和抽取滤波器的设计，完整的工程文件包含： cic_interpolator.mdl cic_decimator.mdl cic_bitwidths.mdl （4）实验分析中的完整工程文件包含： cic_3rd_order.mdl cic_upsampler.mdl-1.1 stage CIC filter design cic_only.mdl ma_only_standard.mdl 2.Multi-stages CIC filter design cic_5th_order_pipe1.mdl cic_5th_order_pipe2.mdl fixed_point_cic.mdl 3)Insert and Decem CIC design cic_interpolator.mdl cic_decimator.mdl cic_bitwidths.mdl
Update : 2025-04-26 Size : 123kb Publisher :
[Software Engineering] CIC-filter DL : 0: 采用多级级联方法降低了对硬件运算速度的要求，有利于实时处理；采用余弦滤波器改善了阻带衰减不足；内插二阶多项式滤波器补偿了 CIC 滤波器通带内的衰减；抗混叠低通滤波器减小了混叠影响-Using multi-stage cascade approach reduces hardware requirements for computing speed, real-time processing in favor cosine filter improves the stop-band attenuation inadequate second-order polynomial interpolation filter compensates for the attenuation of the CIC filter passband anti- aliasing low-pass filter reduces the effects of aliasing
Update : 2025-04-26 Size : 725kb Publisher : xin
[VHDL-FPGA-Verilog] CIC-interpolation-filter DL : 0: 多级插值CIC滤波器，3级、过采样率为2的8位CIC插值滤波器，系统工作时钟的频率是数据速率的2倍 -Multi-stage interpolation CIC filter 3, an oversampling ratio of eight CIC interpolating filter, the operation clock frequency of the system 2 is twice the data rate
Update : 2025-04-26 Size : 1kb Publisher : 刘六