Search - multipliers

[Other resource] booth_mul

Description: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL.
Platform: | Size: 19758 | Author: 李鹏 | Hits:

[Other resource] multipliers

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 7096 | Author: 孙强 | Hits:

[Other resource] VHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642650 | Author: Jawen | Hits:

[ELanguage] and1

Description: 用VHDL语言编写的三位二进制的乘法器，其原理是每位相乘后再错位相加-using VHDL prepared by the three binary multipliers, the principle is that each subsequent dislocation multiplication sum
Platform: | Size: 36528 | Author: yanyuntao | Hits:

[Other resource] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3152400 | Author: Jawen | Hits:

[Other resource] 4mult

Description: 可用的4位乘法器，用VHDL在FPGA中实现-available four multipliers, FPGA VHDL in achieving
Platform: | Size: 1068 | Author: 江良伟 | Hits:

[Windows Develop] MutiplierDesign

Description: 流水线乘法器,vhdl语言描述, 希望对大家有所帮助 -pipelined multipliers, vhdl language, we hope to help
Platform: | Size: 2508 | Author: chenwei | Hits:

[WEB Code] changyongdevhdl

Description: 4位乘法器,4位除法器 8位数据锁存器,8位相等比较器,带同步复位的状态机,元件例化与层次设计,最高优先级编码器-four multipliers, dividers four eight data latches, and eight other phase comparators, synchronous reset with the state machine, the component level with the cases of design, the highest priority encoder
Platform: | Size: 11097 | Author: 刘思雄 | Hits:

[Algorithm] 4mult

Description: 可用的4位乘法器，用VHDL在FPGA中实现-available four multipliers, FPGA VHDL in achieving
Platform: | Size: 1024 | Author: 江良伟 | Hits:

[Other Embeded program] mul8

Description: ieee公布的标准8位浮点乘法器，可综合。采用标准算法。-ieee the standards published by the eight floating-point multipliers, can be integrated. The use of standard algorithm.
Platform: | Size: 2048 | Author: frankey | Hits:

[File Format] applicationofhardwaredescripptionlanguageCVHDLinth

Description: 通过四位乘法器的实例详细介绍了用ＶＨＤＬ语言设计数字系统的流程和方法，通过仿真实现预定目的．-Through the four examples of multipliers detailed design using VHDL language digital system processes and methods, through the simulation to achieve the intended purpose.
Platform: | Size: 157696 | Author: 程军兴 | Hits:

[VHDL-FPGA-Verilog] mul(FLP)

Description: 一个32位元的浮点数乘法器，可将两IEEE 754格式的值进行相乘-A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
Platform: | Size: 2048 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] 0

Description: 用vhdl语言实现4位乘法器，已被测试过，可参考使用-Vhdl language with four multipliers, have been tested, may refer to the use of
Platform: | Size: 1024 | Author: lz | Hits:

[source in ebook] VHDL

Description: VHDL对各种电路的基本实现，包括乘法器，触发器，加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
Platform: | Size: 1138688 | Author: Michael | Hits:

[VHDL-FPGA-Verilog] FIR

Description: The first three examples illustrate the difference between RTL FSMD model (Finite State Machine with Datapath buildin) and RTL FSM + DataPath model. From view of RT level design, each digital design consists of a Control Unit (FSM) and a Datapath. The datapath consists of storage units such as registers and memories, and combinational units such as ALUs, adders, multipliers, shifters, and comparators.
Platform: | Size: 1024 | Author: dhanagopal | Hits:

[VHDL-FPGA-Verilog] 34105908-Multipliers-Using-Vhdl

Description: ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project we compare the working of the three multiplier by implementing each of them separately in FIR filter.
Platform: | Size: 379904 | Author: phitoan | Hits:

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