Search - mux 4 to 1

[Multimedia program] Mux

Description: MPEG4复用层，用VC写的。可以参考以便于学习MPEG-4的协议。-MPEG4 multiplexing layer, with VC writes. In reference to be learning MPEG-4 agreement.
Platform: | Size: 60235 | Author: 石代奎 | Hits:

[Multimedia Develop] Mux

Description: MPEG4复用层，用VC写的。可以参考以便于学习MPEG-4的协议。-MPEG4 multiplexing layer, with VC writes. In reference to be learning MPEG-4 agreement.
Platform: | Size: 60416 | Author: 石代奎 | Hits:

Description: 关于彩信开发的整套文档,有介绍彩信制作的,彩信通信的,彩信解码的,彩信播放的,非常之全面.了解了这些文档,可以开发出彩信软件.-On the MMS to develop the package of documents, there are produced by introduction MMS, multimedia communication, multimedia codecs, and playback MMS, very comprehensive. Understanding of these documents, MMS software can be developed.
Platform: | Size: 1062912 | Author: 黄能辉 | Hits:

[VxWorks] VxWorks_MUX

Description: Vxworks经典论文 VxWorks网络协议栈的MUX接口.pdf 介绍嵌入式实时系统vxworks网络协议栈的MUX接口及其使用方法-Vxworks classic papers VxWorks network protocol stack of MUX interface. Pdf introduction VxWorks embedded real-time system network protocol stack and the MUX interface to use
Platform: | Size: 117760 | Author: GB | Hits:

[Other] MUX

Description: 用CASE实现4选1数据选择器很实用运用VERILOG-Using CASE to achieve 4 election 1 Data Selector practical use Verilog
Platform: | Size: 1024 | Author: 李俊 | Hits:

[VHDL-FPGA-Verilog] Electronic-Design-Automation

Description: 用vhdl语句描述4位等值比较器，4选1多路选择器，8位奇偶校验电路功能-VHDL language used to describe the equivalent four comparators, 4 election more than one MUX, 8-bit parity circuit functions
Platform: | Size: 1024 | Author: 徐靖 | Hits:

[Multimedia Develop] AVIwenjianjiegoushilifenxi

Description: AVI文件结构实例分析——黄东军，贺宏遵文章以二进制打开一个AVI文件详细解释了内部结构-AVI file structure example-黄东军, compliance贺宏article to open a binary file AVI explained in detail the internal structure of
Platform: | Size: 2912256 | Author: cxh | Hits:

[Windows Develop] mux

Description: 4:1 mux test version.
Platform: | Size: 3072 | Author: won ho jung | Hits:

[VHDL-FPGA-Verilog] 4_1

Description: 4 选1 多路选择器-4 to 1 MUX ========
Platform: | Size: 172032 | Author: 彭红 | Hits:

[VHDL-FPGA-Verilog] mux

Description: the multiplexer program are designed 2:1 and 4:1 in verilog model
Platform: | Size: 1024 | Author: prabakaran | Hits:

[VHDL-FPGA-Verilog] finallab

Description: introduction to veri well and behaviural modeling code for 4 to 1 mux
Platform: | Size: 175104 | Author: kaleem | Hits:

[VHDL-FPGA-Verilog] Mux_16to1

Description: Structural of a 16 to 1 MUX (Sixteen 1-bit inputs) that is built * using two 8-to-1 muxes that feed a 2-to-1 mux
Platform: | Size: 9216 | Author: Mohsen | Hits:

[VHDL-FPGA-Verilog] xuanze4x1

Description: 基于VHDL语言 4选1 多路选择器时钟48Mhz 功能4个输入只能有一个输出-Based on VHDL, 4 to 1 MUX clock 48Mhz features 4 inputs can be only one output
Platform: | Size: 144384 | Author: 张帝 | Hits:

[VHDL-FPGA-Verilog] verilog-programs

Description: These are first programs of my asic and fpgas lab.This folder contains simple half adder and its test bench using verilog language.Then it also contains 4 to 1 mux using two 2 to 1 muxes.Then its also has its test bench to check the code.These programs are really help ful for those who want to start the learning of verilog language.
Platform: | Size: 2048 | Author: gul | Hits:

[Streaming Mpeg4] MPEG-2-TS-MUX

Description: 里面都TS mux的资料，从事数字电视的朋友们，可以下载看看，讲述如何进行TS流复用的方法-Inside of the TS mux information in the digital TV friends, you can download to see, how about the TS stream multiplexing method
Platform: | Size: 943104 | Author: 欧阳柏林 | Hits:

[VHDL-FPGA-Verilog] Case-statement-described-4-1-Mux

Description: 用case 语句描述的4 选1 Mux 源码程序，好用--4 with a case statement described 1 Mux source program, easy to use
Platform: | Size: 171008 | Author: 柳勇 | Hits:

[VHDL-FPGA-Verilog] Mux8to1

Description: mux 4 to 1 verilog code. It may be good for you !
Platform: | Size: 4096 | Author: viet | Hits:

[VHDL-FPGA-Verilog] mux

Description: 对20MHZ时钟进行分频。之后用分频后的频率作为时钟信号同步后级的模16计数器。4位计数器输出信号可以用来控制MUX进行数据通道的定时采集。-To 32 magnitude optional 20 MHZ clock frequency division.After using crossover frequency as the clock signal synchronization after level 16 counter modules.Four counter output signal can be used to control the MUX timing acquisition of data channel.
Platform: | Size: 1024 | Author: 曾玉 | Hits:

[Technology Management] mux

Description: mux 4 to 1 in vhdl with generic statement
Platform: | Size: 2048 | Author: nima | Hits:

[VHDL-FPGA-Verilog] mux4_to_1

Description: this files in quartus2 are 4 to 1 mux
Platform: | Size: 2048 | Author: woo | Hits:

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[Multimedia program] Mux

[Multimedia Develop] Mux

[Documents] MMS_PDF

[VxWorks] VxWorks_MUX

[Other] MUX

[VHDL-FPGA-Verilog] Electronic-Design-Automation

[Multimedia Develop] AVIwenjianjiegoushilifenxi

[Windows Develop] mux

[VHDL-FPGA-Verilog] 4_1

[VHDL-FPGA-Verilog] mux

[VHDL-FPGA-Verilog] finallab

[VHDL-FPGA-Verilog] Mux_16to1

[VHDL-FPGA-Verilog] xuanze4x1

[VHDL-FPGA-Verilog] verilog-programs

[Streaming Mpeg4] MPEG-2-TS-MUX

[VHDL-FPGA-Verilog] Case-statement-described-4-1-Mux

[VHDL-FPGA-Verilog] Mux8to1

[VHDL-FPGA-Verilog] mux

[Technology Management] mux

[VHDL-FPGA-Verilog] mux4_to_1

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