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Description: 本程序实现了对输入数路的16选1功能，需要的同志可以研究研究，共同进步-the realization of the import of a number of routes 16 election a function, the comrades need to be studies, and common progress
Platform: |
Size: 88415 |
Author: 龙小军 |
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Description: 本程序实现了对输入数路的16选1功能，需要的同志可以研究研究，共同进步-the realization of the import of a number of routes 16 election a function, the comrades need to be studies, and common progress
Platform: |
Size: 88064 |
Author: 龙小军 |
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Description: VHDL code foe 16:1 MUX using structural modelling
Platform: |
Size: 1024 |
Author: bharat |
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Description: 高速并行，有符号16选一的MUX，完整的VERILOG功能模块和测试平台-High-speed parallel, 16 elections have signed one MUX, a complete functional module and test platform VERILOG
Platform: |
Size: 22528 |
Author: 鲁东 |
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