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[.netStopWatch

Description: 用C#写的跑表,用于学习Timer控件和C#下的stopwatch类,在VS.net 2005下运行通过.-Using C# to write the stopwatch for the study and Timer controls and C# under the stopwatch class, VS.net 2005 in the run through.
Platform: | Size: 38912 | Author: weixin | Hits:

[VHDL-FPGA-Verilogethernet_tri_mode

Description: Its an verilog coded ether net tri mode project
Platform: | Size: 3198976 | Author: apranav | Hits:

[Software EngineeringEAUserGuide

Description: 視覺化的塑模工具,Enterprise Architect這套工具,有支援圖形轉換成10種以上的程式語言(ActionScript、Ada、C and C++、C#、Java、Delphi、Verilog、PHP、VHDL、Python、System、C、VB.Net、Visual Basic)與DDL(SQL script)-Visual modeling tool, Enterprise Architect set of tools, support for graphics into more than 10 species of the programming language (ActionScript, Ada, C and C++, C#, Java, Delphi, Verilog, PHP, VHDL, Python, System, C , VB.Net, Visual Basic) and DDL (SQL script)
Platform: | Size: 20547584 | Author: Yu-Kuang CHUNG | Hits:

[VHDL-FPGA-VerilogVerilog

Description: 在Verilog中有两种类型的赋值语句:连续赋值和过程赋值。赋值表达式由三个部分组成:左值、赋值运算符(=或<=)和右值。右值可以是任何类型的数据,包括net型和register型;但对连续赋值,左值必须是net类型的数据;而过程赋值,左值必须是register类型的数据。下面将作详细描述-There are two types in the Verilog assignment statement: continuous assignment and process assignment. Assignment expression consists of three parts: the left value, the assignment operator (= or < =) and the right values. Right values can be any type of data, including net type and register type but continuous assignment, the left value must be a net type of data the process of assignment, the left value must be a register type of data. Described in detail below
Platform: | Size: 5120 | Author: 林林 | Hits:

[VHDL-FPGA-Verilog(www.entrance-exam.net)-GEN.-APP

Description: verilog hdl code for speed control of dc motor
Platform: | Size: 406528 | Author: syed rafeh hussaini | Hits:

[source in ebookkey

Description: PS2键盘协议代码 verilog,可以在ISE上跑,约束条件:NET"F50M" LOC="B8" NET"ps2_clk" LOC="R12" NET"ps2_data" LOC="P11" NET"rst" LOC="H13" NET"seg[6]" LOC="L18" NET"seg[5]" LOC="F18" NET"seg[4]" LOC="D17" NET"seg[3]" LOC="D16" NET"seg[2]" LOC="G14" NET"seg[1]" LOC="J17" NET"seg[0]" LOC="H14" NET"wei[0]" LOC="F17" NET"wei[1]" LOC="H17" NET"wei[2]" LOC="C18" NET"wei[3]" LOC="F15" NET"rx232_tx" LOC="P9" -PS2 keyboard verilog
Platform: | Size: 33792 | Author: 刘云 | Hits:

[VHDL-FPGA-VerilogBeautiful Restful API in ASP.Net Core

Description: restfull api for the team to beryfy what is the p[robme
Platform: | Size: 34816 | Author: iad | Hits:

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