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[VHDL-FPGA-Verilog] Qsys_nios2

Description: 本教程使用最新的Quartus 11.0sp1+Nios 11.0sp1开发工具。在最新的Quartus II软件中，使用了全新的Qsys进行SOPC系统的构建。 较之以前版本使用SOPC Builder构建有了很大的不同。 本教程为Altera最新的官方Tutorial。 一步步教你使用Qsys构建Nios II系统，并使用Nios II SBT开发应用程序。-This tutorial uses the latest Quartus 11.0sp1+ Nios 11.0sp1 development tools. In the latest Quartus II software, the use of a new build Qsys the SOPC system. Than the previous version has been using the SOPC Builder to build a big difference. This tutorial Altera' s latest official Tutorial. Step by step to teach you to use Qsys build Nios II system, and use the Nios II SBT application development.
Platform: | Size: 2358272 | Author: | Hits:

[VHDL-FPGA-Verilog] led2

Description: nios ii 流水灯源程序，采用quartus ii 11.0,nios ii 11.0,qsys构建CPU，由本人亲自编写，并下载至电路板验证流水灯成功-nios ii water lights, quartus ii 11.0 nios ii 11.0 qsys build the CPU, I personally prepared and downloaded to the board verification of light water
Platform: | Size: 8006656 | Author: 王超 | Hits:

[Other] Quartus_12.0_Qsys

Description: Quartus II 12.0--Qsys及Nios II Eclipse使用方法及详细设置步骤
Platform: | Size: 13744128 | Author: 朱双兵 | Hits:

[Other Embeded program] MyC2Board_RS232_Test

Description: 这是一个Altera FPGA NIOS II RS232通讯程序。 在Quartus II工程中，用Qsys建立了一个NIOS II为核心的CPU系统，并挂接了一个RS232接口。 在software目录下，有三个工程，一个是用C++类包装的RS232类的Eclipse工程，一个是不用C++类包装的Eclipse工程，还有一个是用VC++2008编写的RS232测试工程。 VC++2008编写的工程运行在PC机上，与FPGA中的NIOS II通讯。 这个实验的主要目的是编写一个通用RS232类，这个类即可以用于NIOS II，又可以用于PC机，是一个可重用的RS232类；我们用这个类开发了不少以PC为控制平台，FPGA为硬件控制器的测试系统。 -This is an Altera FPGA NIOS II RS232 communication project. In the Quartus II project, there is a NIOS II CPU with RS232. In the Software directory, there are 3 projects. First one is an Eclipse Project with C++ RS232 Class. Second one is an Eclipse Project with C RS232.h. Other one is a VC++2008 Project with C++ RS232 Class. The purpose of this project is to write a RS232 Class use on any system needed RS232 communication. The RS232 Class not only use on NIOS II, but also use on PC. We used this RS232 Class on many Test Systems with PC and FPGA
Platform: | Size: 13864960 | Author: li hui xian | Hits:

[Other] NIOSII_Qsys_EP4CE15_v1.1.2

Description: Quartus II11.0中，已使用Qsys代替SOPC Builder,是以后Nois开发的一个趋势-instead of SOPC Builder in Quartus II，It s important to Nios II
Platform: | Size: 11685888 | Author: guankun | Hits:

[source in ebook] uart

Description: FPGA uart 通讯 NIOS II QSYS-FPGA uart communication
Platform: | Size: 12282880 | Author: xuwenqing | Hits:

[VHDL-FPGA-Verilog] flash

Description: fpga nios ii vhdl qsys
Platform: | Size: 3895296 | Author: xuwenqing | Hits:

[Other] NIOSII-Qsys_v1.3.1

Description: 黑金刚FPGA开发板使用说明文档，讲诉了NIOS和Qsys的详细开发步奏，值得学习。-KINGBOX FPGA development board documentation, recounts in detail the development of step-outs and Qsys NIOS, it is worth learning.
Platform: | Size: 18086912 | Author: luohui | Hits:

[VHDL-FPGA-Verilog] nios_EPCS_SDRAM

Description: 基于niso ii 13.1开发的测试系统，使用QSYS设计了硬件系统，包含了全部模块，在硬件基础上开发了相应的软件，测试成功了epcs 和sdram，基于DE2开发板，可以直接使用！大家只需要开发软件即可！-DE2 FPGA NIOS 13.1
Platform: | Size: 24485888 | Author: 黄海岸 | Hits:

[VHDL-FPGA-Verilog] ReadFifo

Description: QuartusII 15.0版本中，在Qsys中建立的自己定制的符合Avalon总线协议的IP核，实现功能将输入的TS流识别并存储到FIFO中，Nios核再通过总线对数据进行读取-QuartusII 15 version of the Qsys in to establish their own custom Avalon bus protocol in line with the IP core, the realization of the function to enter the TS stream to identify and store the Nios, FIFO kernel and then read the data through the bus
Platform: | Size: 73728 | Author: 艾馨 | Hits:

[VHDL-FPGA-Verilog] Quartus_II_12.0PQsys_Nios_II

Description: 特权同学经典教程，《Quartus_II_12.0+Qsys及Nios_II教程》,需要的同学赶快来下载吧。-Privileged students Tutorial classic, Quartus II 12.0+ Qsys and Nios II Course , students need to hurry to download it.
Platform: | Size: 1585152 | Author: lupengfei | Hits:

[Other Embeded program] udp_offload

Description: altera udp 开发参考，ep3c120f720c7，内涵qsys系统，nios 代码-altera udp Development Reference, ep3c120f720c7, connotation qsys system, nios Code
Platform: | Size: 166912 | Author: wsc | Hits:

[VHDL-FPGA-Verilog] mt9d112_ddr2

Description: 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory data write and storage, qsys system structures, FPGA and NIOS II joint design
Platform: | Size: 39202816 | Author: 豪 | Hits:

[Embeded-SCM Develop] niosii-triple-speed-ethernet-4sgx230-qsys-141

Description: 利用nios在altera的cyclone4sgx平台上实现一个三态以太网控制器(Implementation of a three state Ethernet controller using Nios)
Platform: | Size: 1133568 | Author: Swaggy | Hits:

[Embeded-SCM Develop] CoreCourse_GHRD_第一课

Description: 这是小梅哥的qsys开发教程中的源码。这是第一课的开发源码。(DESCRIPTION: Simple program that prints "Hello from Nios II" The memory footprint of this hosted application is intended to be small (under 100 kbytes) by default using a standard reference deisgn.)
Platform: | Size: 3663872 | Author: youguess740 | Hits:

[Embeded-SCM Develop] CoreCourse_GHRD_第二课

Description: 这是小梅哥qsys第二课的源码包。这些资料提供给大家学习交流之用。(Processor nios2 Nios II 13.0 All Components nios2 altera_nios2_qsys 13.0 sdram altera_avalon_new_sdram_controller 13.0.1 uart_0 altera_avalon_uart 13.0.1 pio_led altera_avalon_pio 13.0.1 pio_key altera_avalon_pio 13.0.1 ir_decode ir_decode 1.0 altpll_0 altpll 13.0)
Platform: | Size: 4083712 | Author: youguess740 | Hits:

[Embeded-SCM Develop] CoreCourse_GHRD_第三课

Description: 这是小梅哥的qsys学习第三课的内容，这些资料供大家学习交流之用。(Processor nios2 Nios II 13.0 All Components nios2 altera_nios2_qsys 13.0 sdram altera_avalon_new_sdram_controller 13.0.1 uart_0 altera_avalon_uart 13.0.1 pio_led altera_avalon_pio 13.0.1 pio_key altera_avalon_pio 13.0.1 ir_decode ir_decode 1.0 altpll_0 altpll 13.0)
Platform: | Size: 10109952 | Author: youguess740 | Hits:

[Embeded-SCM Develop] CoreCourse_GHRD_第四课1

Description: 这些资料是小梅哥qsys学习第四课第1部分的资料，这些资料供大家学习交流之用。(Processor nios2 Nios II 13.0 All Components nios2 altera_nios2_qsys 13.0 sdram altera_avalon_new_sdram_controller 13.0.1 uart_0 altera_avalon_uart 13.0.1 pio_led altera_avalon_pio 13.0.1 pio_key altera_avalon_pio 13.0.1 ir_decode ir_decode 1.0 altpll_0 altpll 13.0)
Platform: | Size: 5862400 | Author: youguess740 | Hits:

[VHDL-FPGA-Verilog] niosii-triple-speed-ethernet-4sgx230-qsys-131

Description: Altera公司出的三速以太网例程，工程编译完了可以用niosii直接生成simple_socket_server，希望有用。(Altera company out of the three speed Ethernet routines, engineering finished, you can directly generate simple_socket_server using NiosII, I hope useful.)
Platform: | Size: 1160192 | Author: xxswwq | Hits:

[VHDL-FPGA-Verilog] i2c_master_ip_for_nios

Description: i2c master ip for altera nios, add in qsys
Platform: | Size: 218112 | Author: kevinfeng83 | Hits:
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