Search - not gate

[GDI-Bitmap] Java门电路画图器

Description: Java门电路画图器基本功能： 1。文件的保存，打开； 2。添加基本元件； 3。元件的配置用XML保存，不用修改程序即可增加，修改，删除基本元件 4。画点，画线，字符； 5。删除元件 6。统计元件画好的电路用xml文件保存，基本元件的配置也是使用xml文件这个软件虽然小，但是涉及了很多知识，对学Java的初学者还是很有帮助的。文件的保存，单个门电路的保存都是用XML文件存储，使用了线程... 虽然是一个画门电路的软件，但是纯粹是一个Java程序，和门电路没有什么关系的-Java gate drawing for basic functions : 1. Document storage, open; 2. Add the basic components; 3. The configuration of components using XML preservation, can not amend, modify or delete four basic components. Painting, line drawing, character; 5. 6 delete components. Statistics drawn up circuit components used xml document preservation, the basic configuration of the components is the use of the software xml document Although small, but involves a lot of knowledge, to learn Java beginners or very helpful. Document storage, a single gate is used to preserve the XML document storage, the use of the threads ... is a painting gates of software, but is purely a Java program, and the gates of nothing
Platform: | Size: 108394 | Author: 一心一意 | Hits:

[Other resource] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6634118 | Author: 穆群生 | Hits:

[JSP/Java] Java LogicGate

Description: 一个JAVA源程序，用面向对象方法开发和设计的，JAVA的4种逻辑门的设计AND，OR，NOT，XOR-a source Java, Object-oriented development and design. JAVA four logic gate design AND, OR, NOT and XOR
Platform: | Size: 3686 | Author: Mike | Hits:

[OpenGL program] g3DGMV-0

Description: 超强的三为OpenGL渲染渊代码，这点收操能够 VC 6.0 平台（文件就是压缩文件，你他吗的肥硕没有，你门高个屁啊，网页他么的都做不好，关门把）-super three Yuan for OpenGL rendering code, This can be plagued parade VC 6.0 platform (document is compressed files, you him? the stout not, you Gate high Ganpi ah, Mody's website he has done well, closing put)
Platform: | Size: 69218 | Author: 按时地方 | Hits:

[Software Engineering] 11111.files

Description: 汽车娱乐电子推动了功能和容量的快速发展，促使设计人员在性能、成本和灵活性上做出综合考虑。与其他汽车电子领域不同，多媒体图形应用高度可视化，其需求多变，在许多情况下甚至还没有建立标准。汽车设计人员需要一个能够提供最灵活、性能最佳而成本可控的解决方案。可编程逻辑，特别是现场可编程门阵列（FPGA）便是这样的解决方案。 -automobile electronic entertainment functions and promote the rapid development of the capacity to promote design in performance, cost and flexibility make comprehensive consideration. And other areas of Automotive Electronics, multimedia graphics application of highly visual, their needs are ever-changing in many cases have not even established standards. Automobile designers need to be able to provide a most flexible, performance and the best cost-controlled solutions. Programmable logic, in particular field programmable gate array (FPGA) is such a solution.
Platform: | Size: 80728 | Author: yaoming | Hits:

[Software Engineering] DJDPLV_LWB

Description: 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计，不但具有较高的测量精度，而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量，在前端输入加整形电路即可。-use ultra-high-speed Hardware Description Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be.
Platform: | Size: 30945 | Author: 刘刚 | Hits:

[Embeded-SCM Develop] parkguids

Description: 公园导游图数据结构课程设计作业需要的人下功能：给出一张某公园的导游图，游客通过终端询问可知：从某一景点到另一景点的最短路径。游客从公园大门进入，选一条最佳路线，使游客可以不重复地游览各景点，最后回到出口（出口就在入口旁边）。-park guide map data structure curriculum design requires a person under functions : Zhang is a park guide map, asked tourists through the terminal known : from one attraction to another attraction of the shortest path. Park visitors from entering the gate, an election the best route, so that tourists can not repeat visit to the attractions, Finally back to exports (exports next to the entrance).
Platform: | Size: 3227 | Author: 吉庆 | Hits:

[Other] execRing0CodebyAnyUserMode

Description: 众所周知在非 Admin 用户模式下，是不允许加载驱动执行 RING 0 代码的。本文提供了一种方法，通过修改系统 GDT，IDT 来添加自己的 CALLGATE 和 INTGATE 这样便在系统中设置了一个后门。我们就可以利用这个后门在任意用户模式下执行 ring 0 代码了。为了保证我们添加的 CALLGATE 和 INT GATE 永久性。可以在第一次安装时利用 SERVICE API 或 INF 文件设置成随系统启动。不过此方法也有个缺陷，就是在第一次安装 CALLGATE 或 INTGATE 时仍然需要 ADMIN 权限。下面分别给出了添加 CALLGATE 与 INTGATE 的具体代码。 -As is well known in the non-Admin user mode, is not allowed to drive the implementation of load code RING 0. This article provides a method by modifying the system, GDT, IDT to add your own CALLGATE and INTGATE this way in the system set up a backdoor. We can use this backdoor in any user mode implementation of ring 0 code. In order to ensure we add CALLGATE and INTGATE permanent. Can be installed in the first use of SERVICE API or INF file with the system set to start. But this method also has a defect is first installed CALLGATE or INTGATE still need ADMIN privileges. , Respectively, are given below to add CALLGATE with INTGATE specific code.
Platform: | Size: 4096 | Author: Michael | Hits:

[matlab] guid

Description: IC TESTER CODE for OR GATE, AND GATE, NOT GATE
Platform: | Size: 5301248 | Author: amnai11 | Hits:

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[GDI-Bitmap] Java门电路画图器

[Other resource] VHDL语言100例详解

[JSP/Java] Java LogicGate

[OpenGL program] g3DGMV-0

[Software Engineering] 11111.files

[Software Engineering] DJDPLV_LWB

[Embeded-SCM Develop] parkguids

[Other] execRing0CodebyAnyUserMode

[Game Engine] jdnsServer

[VHDL-FPGA-Verilog] VHDLcode_gate

[VHDL-FPGA-Verilog] and_gate

[Software Engineering] APT9302

[VHDL-FPGA-Verilog] basic_gate

[Other Embeded program] Transistor-NOT-Gate

[Software Engineering] shymd

[SCM] test--and-gate-or-gate-not-gate

[matlab] tamrin1-2-AND_OR_NOT

[Linux-Unix] clk-gate

[Other] Gates Using Switch

[matlab] guid

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