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[Communication] 串口通讯JustinIO DL : 0: using System using System.Runtime.InteropServices namespace JustinIO { ?class CommPort { ??public string PortNum ??public int BaudRate ??public byte ByteSize ??public byte Parity // 0-4=no,odd,even,mark,space ??public byte StopBits // 0,1,2 = 1, 1.5, 2 ??public int ReadTimeout ?? ??//comm port win32 file handle ??private int hComm = -1 ?? ??public bool Opened = false ?? ??//win32 api constants ??? private const uint GENERIC_READ = 0x80000000 ??? private const uint GENERIC_WRITE = 0x40000000 ??? private const int OPEN_EXISTING = 3 ?? ??? private const int INVALID_HANDLE_VALUE = -1 -using System using System.Runtime.InteropServices Namespace JustinIO {? Class CommPort { ? ? Public string PortNum? ? Public int BaudRate? ? Public byte ByteSize? ? Public byte Parity // 0-4=no, odd, even, mark, space? ? Public byte StopBits // 0,,1,2 = 1, 1.5, 2? ? Public int ReadTimeout? ? ? ? //comm port win32 file handle? ? Private int hComm =-1? ? ? ? Public bool Opened = false? ? ? ? //win32 api constants? ? ? Private const uint GENERIC_READ = 0x80000000? ? ? Private const uint GENERIC_WRITE = 0x40000000? ? ? Private const int OPEN_EXISTING = 3? ? ? ? ? Private const int INVALID_HANDLE_VALUE =-1? ?
Date : 2025-07-13 Size : 9kb User : liucheng
[MiddleWare] fre_division DL : 0: 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频-Prepared using the Verilog divider, including odd and even sub-sub-band frequency can be arbitrary odd-even frequency
Date : 2025-07-13 Size : 2kb User : 牧云
[VHDL-FPGA-Verilog] clock_divider DL : 0: 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed description of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL examples)
Date : 2025-07-13 Size : 23kb User : xiang
[VHDL-FPGA-Verilog] counter DL : 0: 实现任意奇数偶数分频的模块，而且占空比为50 ，本人一直在用，很好用！-Implementation of arbitrary even-numbered odd-numbered frequency sub-module
Date : 2025-07-13 Size : 1kb User : lee gilbert
[Other] SATAGold DL : 0: sata hdd or ODD is good spec and keyparts
Date : 2025-07-13 Size : 6.13mb User : ll
[Other] odd-even-sort.pdf DL : 0: Odd even sort with mpi
Date : 2025-07-13 Size : 3kb User : renatope30003
[assembly language] even-odd DL : 0: program to count even & odd numbers
Date : 2025-07-13 Size : 46kb User : Gangadhar
[VHDL-FPGA-Verilog] dividerverilogdesign DL : 0: verilog 分频器设计偶数分频器和奇数分频器-divider verilog design even and odd divider divider
Date : 2025-07-13 Size : 10kb User : lulu
[VHDL-FPGA-Verilog] Odd-number-frequency-division DL : 0: 在FPGA中对系统时钟进行奇数分频程序，可适当改变参数对其进行任意奇数分频 verilog HDL语言-Odd number frequency division program based on FPGA
Date : 2025-07-13 Size : 329kb User : yzy
[VHDL-FPGA-Verilog] div_frequency DL : 0: 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
Date : 2025-07-13 Size : 1kb User : ye
[VHDL-FPGA-Verilog] dividing-an-odd-number- DL : 0: Verilog语言实现奇数分频1比1；简单易实现。-Verilog realize dividing an odd number 1-1 Simple easy to realize.
Date : 2025-07-13 Size : 1kb User : maochiheng
[matlab] coupler-even-odd DL : 0: Coupler even odd :Shows how to calculate the even and odd modes of a pair of two adjacent coupled identical waveguides.
Date : 2025-07-13 Size : 5kb User : saragih
[Other systems] even-odd DL : 0: print even and odd numbers
Date : 2025-07-13 Size : 8kb User : masood
[MPI] odd-even-transpostion DL : 0: An odd-even transposition program using Intel MPI and OpenMP
Date : 2025-07-13 Size : 3kb User : MegaStone
[Delphi VCL] An-odd-number-of-sum DL : 0: Delphi写的输入两个整数，求出这两个数之间所有奇数之和。-Delphi written input two integers, all odd numbers between the two numbers is obtained.
Date : 2025-07-13 Size : 9kb User : id53634v
[Special Effects] odd DL : 0: 这是图像处理中获得奇场矩阵的最基本也最实用的函数，很值得一看。-This is an odd field image processing to obtain the most basic and most useful matrix functions, it is worth a visit.
Date : 2025-07-13 Size : 1kb User : 林
[VHDL-FPGA-Verilog] Odd-Frequence-Dividing-Circuit DL : 0: 一种奇数分频电路的设计方法，采用verilog HDL描述。修改代码中参数可以进行任意奇数分频，包含了设计文档和源代码。-A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
Date : 2025-07-13 Size : 94kb User : zhouwen
[File Format] odd-and-event-flashing-led DL : 0: This file contains a simple program on the program the LED lights turn on odd and even. We use a 16F84 PIC microcontroller, the PIC BASIC Pro for programming languages .
Date : 2025-07-13 Size : 29kb User : gani
[File Format] odd-flashing-led DL : 0: This file contains a simple program on the LED lights lit odd program. We use a 16F84 PIC microcontroller, the PIC BASIC Pro for programming languages .
Date : 2025-07-13 Size : 29kb User : gani
[Game Program] judgment-even-and-odd DL : 0: 用三元运算符判断奇数和偶数,比较小，哈哈哈哈，谁让你们命名不能超过20个字符啊-With ternary operator judgment even and odd
Date : 2025-07-13 Size : 6kb User : li

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