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[Communication] 串口通讯JustinIO

Description: using System using System.Runtime.InteropServices namespace JustinIO { ?class CommPort { ??public string PortNum ??public int BaudRate ??public byte ByteSize ??public byte Parity // 0-4=no,odd,even,mark,space ??public byte StopBits // 0,1,2 = 1, 1.5, 2 ??public int ReadTimeout ?? ??//comm port win32 file handle ??private int hComm = -1 ?? ??public bool Opened = false ?? ??//win32 api constants ??? private const uint GENERIC_READ = 0x80000000 ??? private const uint GENERIC_WRITE = 0x40000000 ??? private const int OPEN_EXISTING = 3 ?? ??? private const int INVALID_HANDLE_VALUE = -1 -using System using System.Runtime.InteropServices Namespace JustinIO {? Class CommPort { ? ? Public string PortNum? ? Public int BaudRate? ? Public byte ByteSize? ? Public byte Parity // 0-4=no, odd, even, mark, space? ? Public byte StopBits // 0,,1,2 = 1, 1.5, 2? ? Public int ReadTimeout? ? ? ? //comm port win32 file handle? ? Private int hComm =-1? ? ? ? Public bool Opened = false? ? ? ? //win32 api constants? ? ? Private const uint GENERIC_READ = 0x80000000? ? ? Private const uint GENERIC_WRITE = 0x40000000? ? ? Private const int OPEN_EXISTING = 3? ? ? ? ? Private const int INVALID_HANDLE_VALUE =-1? ?
Platform: | Size: 9216 | Author: liucheng | Hits:

[MiddleWare] fre_division

Description: 使用verilog编写分频器，包括奇分频和偶分频，可以进行任意奇偶分频-Prepared using the Verilog divider, including odd and even sub-sub-band frequency can be arbitrary odd-even frequency
Platform: | Size: 2048 | Author: 牧云 | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: 任意小数分频器产生原理，及详细说明文档，任意数分频(包括奇偶数和小数)的设计方法(含VHDL例子)-Generate arbitrary decimal divider principle, and detailed description of the document, arbitrary number of sub-frequency (including the odd-even numbers and decimals) design methods (including VHDL examples)
Platform: | Size: 23552 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] counter

Description: 实现任意奇数偶数分频的模块，而且占空比为50 ，本人一直在用，很好用！-Implementation of arbitrary even-numbered odd-numbered frequency sub-module
Platform: | Size: 1024 | Author: lee gilbert | Hits:

[Other] SATAGold

Description: sata hdd or ODD is good spec and keyparts
Platform: | Size: 6430720 | Author: ll | Hits:

[Other] odd-even-sort.pdf

Description: Odd even sort with mpi
Platform: | Size: 3072 | Author: renatope30003 | Hits:

[assembly language] even-odd

Description: program to count even & odd numbers
Platform: | Size: 47104 | Author: Gangadhar | Hits:

[VHDL-FPGA-Verilog] dividerverilogdesign

Description: verilog 分频器设计偶数分频器和奇数分频器-divider verilog design even and odd divider divider
Platform: | Size: 10240 | Author: lulu | Hits:

[VHDL-FPGA-Verilog] Odd-number-frequency-division

Description: 在FPGA中对系统时钟进行奇数分频程序，可适当改变参数对其进行任意奇数分频 verilog HDL语言-Odd number frequency division program based on FPGA
Platform: | Size: 336896 | Author: yzy | Hits:

[VHDL-FPGA-Verilog] div_frequency

Description: 任意分频器，用Verilog HDL实现，只需修改参数可以实现奇数、偶数分频，FPGA应用必备资料。-Any divider, using Verilog HDL to achieve, simply modify the parameters can be achieved odd, even frequency, FPGA applications necessary information.
Platform: | Size: 1024 | Author: ye | Hits:

[VHDL-FPGA-Verilog] dividing-an-odd-number-

Description: Verilog语言实现奇数分频1比1；简单易实现。-Verilog realize dividing an odd number 1-1 Simple easy to realize.
Platform: | Size: 1024 | Author: maochiheng | Hits:

[matlab] coupler-even-odd

Description: Coupler even odd :Shows how to calculate the even and odd modes of a pair of two adjacent coupled identical waveguides.
Platform: | Size: 5120 | Author: saragih | Hits:

[Other systems] even-odd

Description: print even and odd numbers
Platform: | Size: 8192 | Author: masood | Hits:

[MPI] odd-even-transpostion

Description: An odd-even transposition program using Intel MPI and OpenMP
Platform: | Size: 3072 | Author: MegaStone | Hits:

[Delphi VCL] An-odd-number-of-sum

Description: Delphi写的输入两个整数，求出这两个数之间所有奇数之和。-Delphi written input two integers, all odd numbers between the two numbers is obtained.
Platform: | Size: 9216 | Author: id53634v | Hits:

[Special Effects] odd

Description: 这是图像处理中获得奇场矩阵的最基本也最实用的函数，很值得一看。-This is an odd field image processing to obtain the most basic and most useful matrix functions, it is worth a visit.
Platform: | Size: 1024 | Author: 林 | Hits:

[VHDL-FPGA-Verilog] Odd-Frequence-Dividing-Circuit

Description: 一种奇数分频电路的设计方法，采用verilog HDL描述。修改代码中参数可以进行任意奇数分频，包含了设计文档和源代码。-A design of odd frequence dividing circuit is presented, which is described by verilog HDL。Change the parameter in code, one can get any odd numbers of frequence dividing circuit.
Platform: | Size: 96256 | Author: zhouwen | Hits:

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