Search - odd counter

Search - odd counter - List

[Other resource] sanfenpin DL : 0: 这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside the N and counter can be amended
Date : 2008-10-13 Size : 645.59kb User : magma1981
[VHDL-FPGA-Verilog] sanfenpin DL : 0: 这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside the N and counter can be amended
Date : 2025-07-13 Size : 645kb User : magma1981
[VHDL-FPGA-Verilog] counter DL : 0: 实现任意奇数偶数分频的模块，而且占空比为50 ，本人一直在用，很好用！-Implementation of arbitrary even-numbered odd-numbered frequency sub-module
Date : 2025-07-13 Size : 1kb User : lee gilbert
[VHDL-FPGA-Verilog] odd DL : 0: 6分频的一个工程文件 altera 分配计数器的源码-6 frequency distribution of a project file counter source altera
Date : 2025-07-13 Size : 257kb User : danny
[VHDL-FPGA-Verilog] ass1_2_hamming DL : 0: Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a Veriog module for generating pseudorandom 4-bit data using Linear Feedback Shift Register( LFSR) method. c) Develop a Verilog module to emulate one bit error in the data transmission. This can be done by changing only one of the encoded bits at each clock cycle. You may use a ring-counter and XOr gates for doing this. This arrangement will insert error in consecutive bits at each clock cycle. d) Design a Hamming error detection and correction circuit to restore the original data. e) Compare the original data with the restored data to verify the error correction capability of your design. If the two data sets are equal an OK signal will be set.
Date : 2025-07-13 Size : 1.08mb User : wei chenghao
[VHDL-FPGA-Verilog] fenpinqi-VerilogHDL DL : 0: 各种分频器的VerilogHDL语言编写，有通过计数器实现的奇分频，偶分频，任意分频-Various divider VerilogHDL language, there is achieved through the odd frequency counter, even frequency, any frequency
Date : 2025-07-13 Size : 2kb User : 王体奎
[Embeded-SCM Develop] 7seg-counter DL : 0: up ,down ,odd and even counter using 7segment ,lcd and 80c535 ic
Date : 2025-07-13 Size : 63kb User : aala
[VHDL-FPGA-Verilog] state10 DL : 0: VHDL 三、五奇数模计数器占空比0.5-VHDL counter odd mode duty cycle 0.5
Date : 2025-07-13 Size : 185kb User : Wang
[VHDL-FPGA-Verilog] divider DL : 0: 使用模为2N+1的计数器,让输出时钟在X-1(X在0到2N-1之间)和2N时各翻转一次,则可得到奇数分频器,但是占空比并不是50 -The use of modulo 2N+1 counter, let the output clock in the X-1 (X between 0 and 2N-1) and 2N of the turning once, then can get the odd divider, but the duty ratio is not 50
Date : 2025-07-13 Size : 1kb User : houxili