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[ARM-PowerPC-ColdFire-MIPS] uCOSII_FS44b0x

Description: 1）通过fs44b0xbios和网口，将upload里的boot.bin烧写到flash 0 地址 见“FS44B0Xbios使用指南”之5 2) 打开57600超级终端 3) 连上串口线和jtag调试头 4）打开FS44B0X开发板电源 5）运行jtag.exe,在SDT下调入 ucosii_demo.axf，运行 6) 在超级终端上有三个任务的运行与退出显示，板子上的三个发光二极管会来回闪烁。 -a) fs44b0xbios and LAN, li will upload the burning of flash boot.bin 0 addresses see "FS44B0Xbio s User's Guide "5 2) to open 57,600 Super Terminal 3) connected to serial lines and the first four JTAG Debugging) Open FS44B0X development board Power 5) Run jtag.exe, under the redeployment ucosii_demo.axf SDT, running 6) of the Super Terminal 3 on the mandate of the operation and withdraw from the show, on board the three light-emitting diodes will flicker back and forth.
Platform: | Size: 215040 | Author: 张淼林 | Hits:

[VHDL-FPGA-Verilog] OpenRISC

Description: 一个开放的risc，已应用到实际中，可以借鉴的不少，大家-an open RISC, has been applied to practice, we can draw a lot, we look at
Platform: | Size: 2586624 | Author: 12 | Hits:

[VHDL-FPGA-Verilog] OR1200_verilog

Description: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Platform: | Size: 204800 | Author: yu | Hits:

[VHDL-FPGA-Verilog] sparc_verilog

Description: open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
Platform: | Size: 214016 | Author: 王翔 | Hits:

[Other Embeded program] 1160037925_1_FT224_iso7816_vcc

Description: iso7816_plain.c implements an interface between an RS-232 serial port and an ISO 7816 smart card, and is targeted for the Atmel AT90S2313 microcontroller in a development terminal. The source code is written entirely in C using the WinAVR tool suite. WinAVR is a suite of executable, open source software development tools for the Atmel AVR series of RISC microcontrollers hosted on the Windows platform. It includes the GNU GCC compiler (avr-gcc) for C and C++. WinAVR is provided free of charge.
Platform: | Size: 8192 | Author: Subramanyam | Hits:

[VHDL-FPGA-Verilog] Simply-RISC-S1-Source-code

Description: 开源可扩充处理器架构，源代码，用来查询非常好，值得下载。-The open-source extensible processor architecture, used to query the source code, very good, it is worth to download
Platform: | Size: 1428480 | Author: 杨金谕 | Hits:

[VHDL-FPGA-Verilog] or1200_ep3c16_board

Description: OpenRisc是OpenCores组织提供的基于GPL协议的开放源代码的RISC（精简指令集计算机）处理器。有人认为其性能介于ARM7和ARM9之间，适合一般的嵌入式系统使用。最重要的一点是OpenCores组织提供了大量的开放源代码IP核供研究人员使用，因此对于一般的开发单位具有很大的吸引力。-OpenRisc is based organizations OpenCores the GPL open source RISC (Reduced Instruction Set Computer) processor. Some people think that the performance between the ARM7 and ARM9, an embedded system for general use. The most important point is OpenCores organization provides a number of open-source IP cores for researchers to use, so for the average developer is very attractive.
Platform: | Size: 260096 | Author: 程浩武 | Hits:

[VHDL-FPGA-Verilog] S1 CPU core

Description: S1 Core (codename Sirocco) is an open source hardware microprocessor design developed by Simply RISC. Based on Sun Microsystems' UltraSPARC T1, the S1 Core is licensed under the GNU General Public License, which is the license Sun chose for the OpenSPARC project.
Platform: | Size: 1114206 | Author: xptogudovan | Hits:

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