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[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

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