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[SCM] MCUTool

Description: 单片机开发过程中用到的多功能工具，包括热敏电阻RT值--HEX数据转换；3种LED编码；色环电阻计算器；HEX/BIN 文件互相转换；eeprom数据到C/ASM源码转换；CRC校验生成；串口调试，带简单而实用的数据分析功能；串口/并口通讯监视等功能. 用C++ Builder开发，无须安装，直接运行，不对注册表进行操作。纯绿色软件。-microcontroller used in the process of developing the multi-purpose tools, including a thermistor RT value-- HEX data conversion; Three LED coding; Color Central Resistance calculator; HEX/BIN documents interchangeable; EEPROM data to the C/ASM source code conversion; CRC generation; Serial debugging, with a simple and practical data analysis functions; Serial/Parallel Communications surveillance capabilities. C Builder development without installing, operating directly, and do not operate the registry. Green pure software.
Platform: | Size: 443392 | Author: | Hits:

[VHDL-FPGA-Verilog] GenCrc1

Description: 并口硬盘标准PATA6的CRC效验码的vhdl代码-Parallel hard disk standard PATA6 the CRC code well-tested code vhdl
Platform: | Size: 1024 | Author: hy | Hits:

[Crack Hack] parallel_CRC

Description: CRC校验并行实现,Verilog源码.8位数据输入,实现速度快,适用与各种类型的器件.-Parallel Implementation of CRC checksum, Verilog source code .8-bit data input, to achieve fast, applicable with all types of devices.
Platform: | Size: 78848 | Author: 徐亮 | Hits:

[Crack Hack] crc

Description: 用于10M，100M，1000M以太网的并行CRC算法，有别于一般的CRC算法。verilog描述-For 10M, 100M, 1000M Ethernet parallel CRC algorithm, the CRC algorithm is different from the ordinary. Verilog Description
Platform: | Size: 1024 | Author: winwalk | Hits:

[Post-TeleCom sofeware systems] crc32

Description: --循环冗余计算的并行实现代码 --初始值是全0或全1都可以-Cyclic redundancy code realize parallel computing the initial value is 0 or 1 whole can be
Platform: | Size: 1024 | Author: luvicee | Hits:

[ARM-PowerPC-ColdFire-MIPS] crc16_8bit.v

Description: 利用verilog硬件描述语言编写的8为并行输入的常crc校验模块。hdlc子模块-Using Verilog hardware description language for the parallel importation of 8 regular CRC checksum module. HDLC sub-modules
Platform: | Size: 1024 | Author: 张纪强 | Hits:

[Other] CRC_Parallel_Computation_Implementation_on_FPGA.ra

Description: CRC校验码并行计算的FPGA实现,PDF打开-CRC Check Code FPGA realize parallel computing, PDF to open
Platform: | Size: 231424 | Author: pipi_dog | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
Platform: | Size: 934912 | Author: sunlee | Hits:

[Crack Hack] crc16

Description: CRC16的源程序，实现crc校验，并行crc校验-CRC16 source, the realization of CRC checksum, parallel CRC Checksum
Platform: | Size: 878592 | Author: hent | Hits:

[Software Engineering] CRC

Description: 　本文提出一种通用的CRC 并行计算原理及实现方法,适于不同的CRC 生成多项式和不同并行度(如8 位、16 位、及32 位等) ,与目前已采用的查表法比较,不需要存放余数表的高速存储器,减少了时延,且可通过增加并 行度来降低高速数传系统的CRC 运算时钟频率.-In this paper, a universal principle of CRC and implementation of parallel computing methods for generating different CRC polynomial and different degree of parallelism (eg, 8, 16, and 32-bit, etc.), with the current look-up table method has been used in comparison do not store more than a few tables, high-speed memory, reducing latency, and degree of parallelism can be increased to reduce the high-speed data-transmission system clock frequency of the CRC computation.
Platform: | Size: 144384 | Author: 黑月 | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
Platform: | Size: 752640 | Author: heshuiming | Hits:

[VHDL-FPGA-Verilog] CRC_16

Description: crc16的串行和并行写法，而且有详细的测试文件-Serial and parallel crc16 written, and detailed test documents
Platform: | Size: 20480 | Author: Jammy | Hits:

[Crack Hack] Crc_Parallel

Description: CCITT Parallel CRC 16-bit
Platform: | Size: 1024 | Author: timngo | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[Other] crc

Description: crc的原理以及格式，和并行crc的代码．另外一个是rfid的协议标准-crc datasheet and parallel code design. another pdf is rfid 14443 spec chinese version.
Platform: | Size: 331776 | Author: 老六 | Hits:

[VHDL-FPGA-Verilog] parallel_CRC_code

Description: CRC Generation can be done by using PARALLELISM. Efficient method to calculate CRC in less time. By using more hardware for parallel CRC and obtaining more latency and throughput.
Platform: | Size: 1024 | Author: Sankar MK | Hits:

[VHDL-FPGA-Verilog] eth_crc

Description: crc校验码Verilog 程序。此为4位并行crc——32校验。-crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
Platform: | Size: 2048 | Author: hepeng | Hits:

[VHDL-FPGA-Verilog] UHF-RFID-CRC

Description: 本文首先研究了IsO／IECl8000．6标准中A、B两类短程通讯的前向链路与返回 链路的数据编码方式，对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码 的编解码方式和技术参数进行了深入的分析，并利用FPGA实验平台对这三种编 码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理 进行了探讨，重点研究了ISo／IECl8000．6标准中采用的数据保护与校验技术，即 循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现CRC的电 路，从理论和实现两个方面对其中存在的问题提出了解决办法，设计了一种改进 型线性反馈移位寄存器电路来实现循环冗余校验。对于要求CRC运算速度高的系 统，本文利用了递归的算法设计了一种新型的并行CRC电路。最后本文提出了一 种新颖的UHF RFID系统数字基带电路，区别于一般数字基带电路的地方是：在编 解码模块和CRC模块之间加入了卷积编码和维特比译码模块。利用卷积码优良的 纠错能力，来解决UHF RFID系统在电磁干扰严重的环境中识别率低、通信速度慢 的问题，效果良好。-The first，this paper investigates the f．0rward link and retum link data encodlng method in short range communication types A and B in ISO／IEC 1 8000-6，and deeply analyzes encoding method and technical parameters of Bi—Phase Space(FMO)coding， Pulse IntervaI Encoding(PIE)coding and Manchester coding．We also designed and simulated code circuits and decode circuits of the three encoding method by FPGA experiment platfoml． The second， We discussed the technical principle of error control of the UHF RFID system，especially for the techn0109y of data Verification 肌d calibration，namely cyclic redundancy check that used in IS0／IEC 1 8000·6·The circuits of CRC based on Linear Feedback Shin Register(LSFR)are analyzed行om theonr and realization，and some means of solVing problems are put fon)Irard，then an improved LSFR circuit to implement CRC is designed．For some require fast CRC calculation system，we designed a noVel parallel CRC circuit by using recurslVe fomlula．In the end，we put forw
Platform: | Size: 4366336 | Author: HY jian | Hits:

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

Description: 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based implementations, there are classic serial algorithm LFSR, circuits and software algorithms derived from the other kinds of parallel computing. To the classic LFSR, circuit-based, study by the CRC byte parallel computing principles.
Platform: | Size: 205824 | Author: Geer | Hits:

[VHDL-FPGA-Verilog] parallel-CRC-calculation-in-FPGAs-

Description: 给大家介绍关于crc校验原理和算法。并在fpga实现描述。-To introduce the crc check principle and algorithm。To achieve the description in fpga
Platform: | Size: 92160 | Author: 吴越强 | Hits:
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