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[Software Engineering] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228801 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228352 | Author: yaoming | Hits:

[Other] bingxingfir

Description: 并行匹配滤波器，用于ＣＤＭＡ通信技术中的滤波，滤除无用信号-parallel matched filter for CDMA technology of filtering, signal filtering useless
Platform: | Size: 1024 | Author: 谢金娟 | Hits:

[VHDL-FPGA-Verilog] 8stepSymmetryCoefficientFilter

Description: 8阶对称系数并行FIR滤波器(verilog)用作数字滤波，系数可调。根据实际截止频率决定。-8-order FIR filter symmetric coefficients parallel (verilog) used for digital filtering, adjustable coefficient. Decisions based on the actual cut-off frequency.
Platform: | Size: 1024 | Author: TGY | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[Program doc] Fire_Code(42_33)

Description: 该代码是802.3ap推荐代码fir吗(42,33)的编码器和解码器,该代码采用C语言实现,可以完成译码功能,该代码采用并行编译码方式实现,可以应用于100G以太网的FEC-The code is 802.3ap you recommend fir code (42,33) of the encoder and decoder, the code using C language, you can complete the decoding function, the code achieved by the use of parallel encoding and decoding, can be applied to 100G Ethernet The FEC
Platform: | Size: 565248 | Author: 陈曦 | Hits:

[MPI] GPUFIR

Description: 一个基于GPU运算的FIR滤波器程序，基于CUDA平台而开发。支持GPU并行运算。-GPU-based computing a FIR filter process, developed based on the CUDA platform. Support GPU parallel computing.
Platform: | Size: 306176 | Author: Jim Teoh | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] 65jie

Description: 串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点，但是要占用大量的资源。在多阶数的亚高频系统设计中，使用并行结构并不合算，但亚高频系统需要较高的处理速度，而串行架构往往达不到要求，因此，结合串并这两种设计方法的长处，在使用较少的硬件资源的同时实现了较高的处理速度，这里说明一种65阶八路并行、支路串行FIR滤波器的设计（实际使用了1个乘法器，8个乘累加器，一个累加器）。-String and FIR filter design: parallel FIR filter with a fast, easy design features, but I want to use up a lot of resources. In a multi-order high-frequency sub-system design, the use of parallel structures and uneconomical, but the high frequency sub-system requires a higher processing speed, and the serial structure often fail, therefore, combines both the design of string and method' s strengths, using less hardware resources to achieve a high processing speed of 65 bands here that a parallel eight-way, slip serial FIR filter design (the actual use of a multiplier, 8 by accumulator, an accumulator).
Platform: | Size: 12288 | Author: 南才北往 | Hits:

[Graph program] FIR

Description: 基于并行结构分布式算法的FIR滤波器设计-Distributed algorithm based on parallel structures FIR filter design
Platform: | Size: 232448 | Author: cccl | Hits:

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

Description: 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
Platform: | Size: 1383424 | Author: francis davis | Hits:

[VHDL-FPGA-Verilog] FIR_filter

Description: Parallel FIR filter example. It is low-pass filter for CPLD or FPGA platforms. Project compiled and simulated in Modelsim
Platform: | Size: 237568 | Author: Serg | Hits:

[Other] fir

Description: fir滤波器的几种结构virelog代码（串行，并行，DA结构以及多相抽取结构），程序包为ise工程-fir filter several the structure virelog code (serial, parallel, DA structure and multiphase extraction structure), the program package for the ise project
Platform: | Size: 1005568 | Author: 黄远望 | Hits:

[VHDL-FPGA-Verilog] verilog-fir

Description: 基于verilog的三种不同方式的fir滤波器 fir1:直接型 fir2：串行DA fir3：并行DA-Fir filter for the verilog three different ways fir1: direct type fir2 of: serial of DA fir3: parallel DA
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] DAbx

Description: 基于FPGA的并行FIR数字滤波器的实现-FPGA-based parallel FIR digital filter implementation
Platform: | Size: 4961280 | Author: 林林 | Hits:

[matlab] FIR

Description: FIR滤波器的仿真和实现。包括matlab的仿真文件和基于VHDL语言的硬件实现代码。算法包括串行和并行两种。-Simulation and implementation of FIR filters. Including matlab simulation files and hardware implementation based on VHDL code. Including both serial and parallel algorithms.
Platform: | Size: 526336 | Author: 王大壮 | Hits:

[matlab] E4_8_FirParallel

Description: 无线通信系统FIR MATLAB生成模块。ISE完整工程。 -Parallel FIR MATLAB module for wireless telecom system.ISE full project.
Platform: | Size: 6827008 | Author: 田田 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 利用系数奇对称的性，节约一半乘法器资源，实现平行FIR滤波器的功能。-The function of parallel FIR filter is realized by using oddly symmetric coefficients and saving half of the multiplier resources.
Platform: | Size: 4817920 | Author: lerning dog | Hits:

[Other] VHDL-FIR-filters

Description: ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has been synthesized with Xilinx Vivado 2015.1 to confirm the correct DSP cascade chain is inferred.
Platform: | Size: 37888 | Author: Abkoti | Hits:

[Other] Comparative study of FFA architectures using different multiplier and adder topologies

Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Platform: | Size: 1123027 | Author: nalevihtkas | Hits:
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