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[Parallel Port] e047_pcmciatob

Description: 自制pcmcia并口vhdl代码，及制作所须其他资料.-homemade pcmcia parallel VHDL code and the production of other required information.
Platform: | Size: 3924841 | Author: 孙德黎 | Hits:

[VHDL-FPGA-Verilog] gaxgq16

Description: 16位并行相关器的VHDL程序-16 parallel with the VHDL-related procedures
Platform: | Size: 1024 | Author: 张庆辉 | Hits:

[SCM] vhdl_lcd

Description: 使用C语言与VHDL实现 液晶显示控制器示例使用说明 使用模块有：单片机模块、液晶显示模块。 使用步骤： 1. 打开电源+5V。 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载。 4. 液晶屏上将显示一幅图像。 -use C language and VHDL LCD controller using examples of the use of modules : SCM modules, LCD display modules. Use steps : 1. Turn the power 5V. 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connections and will be loading procedures. 4. LCD screen will show an image.
Platform: | Size: 39936 | Author: 刘浪 | Hits:

[VHDL-FPGA-Verilog] vhdl_vga

Description: 彩条信号发生器使用说明 使用模块有：VGA接口、脉冲沿模块、时钟源模块。 使用步骤： 1. 打开电源+5V 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载。 4. 将彩色显示器的线与VGA接口连接好。 5. 彩条信号就可以在显示器中产生，通过脉冲沿模块按键MS1可以改变产生彩条的 -color of the signal generator for use with the use of modules : VGA, pulse along the module, module clock source. Use steps : 1. Turn the power 5V 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connections and will be loading procedures. 4. Will the line color display with VGA interface connector good. 5. Choi of the signal can be generated in the display, along the pulse button MS1 module can change color of the produce
Platform: | Size: 95232 | Author: 刘浪 | Hits:

[VHDL-FPGA-Verilog] vhdl_LED

Description: 点阵显示实验示例使用说明 使用模块有：时钟源模块、点阵显示模块，脉冲沿模块。 使用步骤： 1. 打开电源+5V。 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载 4. 脉冲沿模块的按键MS1为复位清零键，灯灭时有效，点阵块上会显示汉字。 -lattice experimental use of the use of sample modules : clock source modules, dot-matrix display module, pulse along the module. Use steps : 1. Turn the power 5V. 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connecting lines and procedures for loading 4. Pulse module along the MS1 to reset button, reset button, when the lights were effective, Lattice pieces will be shown on Chinese characters.
Platform: | Size: 333824 | Author: 刘浪 | Hits:

[Parallel Port] e047_pcmciatob

Description: 自制pcmcia并口vhdl代码，及制作所须其他资料.-homemade pcmcia parallel VHDL code and the production of other required information.
Platform: | Size: 3924992 | Author: 孙德黎 | Hits:

[Communication-Mobile] serialparallel

Description: BCH编码器并行8路实现，速率达到300M以上-BCH encoder realize 8-channel parallel, the rate reached more than 300M
Platform: | Size: 2048 | Author: 张凯斌 | Hits:

[Com Port] UARTchuli

Description: UART 处理的是并行数据转换为串行信号和串行信号转换为并行数据。现有的时钟不精确,这就需要用一个远高于波特率的本地时钟信号对输入信号不断采样,以不断让接收器与发送器保持同步。-UART to handle is the parallel data into a serial signal and serial signal is converted to parallel data. Existing imprecise clock, which requires a much higher than the baud rate of the local clock signal for sampling the input signal continuously to continuously allow the receiver to maintain synchronization with the transmitter.
Platform: | Size: 1024 | Author: xuye | Hits:

[VHDL-FPGA-Verilog] 8255_IO_vhdl

Description: VHDL语言设计 8255并行I/O接口芯片-VHDL Language Design 8255 Parallel I/O interface chip
Platform: | Size: 1024 | Author: weixj | Hits:

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

[Com Port] Receiver

Description: This file recieves the serial data from the UART and forward to Serial To Parallel module
Platform: | Size: 2048 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] vhdl-2008-just-the-new-stuff-systems-on-silicon.r

Description: VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual—Amendment 1: Procedural Language Application Interface.
Platform: | Size: 800768 | Author: chane | Hits:

[VHDL-FPGA-Verilog] serial

Description: 串行转并行的VHDL源代码，结构化编程，学习模块化编程和实用性都很大。-Serial transfer parallel VHDL source code, structured programming, modular programming and practical learning are great.
Platform: | Size: 13312 | Author: tangjieling | Hits:

[VHDL-FPGA-Verilog] seriall2parallel

Description: its code for converting serial to parallel processing data
Platform: | Size: 1024 | Author: sundaram | Hits:

[VHDL-FPGA-Verilog] parallel-output-controller-(POC)

Description: 并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provided for simulation.
Platform: | Size: 74752 | Author: 陈鹏 | Hits:

[VHDL-FPGA-Verilog] PARALLEL-MULTIPLIER

Description: vhdl code for a 32 bit parallel multiplier
Platform: | Size: 7168 | Author: sandeep kumar | Hits:

[VHDL-FPGA-Verilog] CRC-Parallel-Computation

Description: 用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based implementations, there are classic serial algorithm LFSR, circuits and software algorithms derived from the other kinds of parallel computing. To the classic LFSR, circuit-based, study by the CRC byte parallel computing principles.
Platform: | Size: 205824 | Author: Geer | Hits:

[VHDL-FPGA-Verilog] vhdl-ad9910

Description: ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers -ad9910 DDS board VHDL source code, in the Cyclone II FPGA debugging through the main file description: Filename Function----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration, opcode definition dds_serial.vhd parallel to serial decoding fifo.vhd FIFO megafunction intance phase_register.vhd phase registers-----------------------------------------------------
Platform: | Size: 93184 | Author: bin | Hits:

[Other] VHDL-FIR-filters

Description: ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has been synthesized with Xilinx Vivado 2015.1 to confirm the correct DSP cascade chain is inferred.
Platform: | Size: 37888 | Author: Abkoti | Hits:

[VHDL-FPGA-Verilog] Serial to parallel vhdl

Description: SERIAL TO PARALLEL VHDL CODE
Platform: | Size: 9216 | Author: kiruthikka | Hits:
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