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Description: PCI驱动编程实例，通过PCI可实施操作：
2、通过DMA方式往SDRAM写数据的步骤：
(1) 往OMB1写传输数据次数
(2) 往OMB2写所要访问的SDRAM地址
(3) 往FIFO写2
3、通过DMA方式从SDRAM读数据的步骤：
(1) 往OMB1写传输数据次数
(2) 往OMB2写所要访问的SDRAM地址
(3) 往FIFO写3
-PCI-driven programming examples, can be implemented through the PCI operation : 2, DMA SDRAM write data to the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to FIFO write 2 3 through DMA side SDRAM-time data from the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to write FIFO 3
Platform: |
Size: 62751 |
Author: 葛琳 |
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Description: PCI驱动编程实例，通过PCI可实施操作：
2、通过DMA方式往SDRAM写数据的步骤：
(1) 往OMB1写传输数据次数
(2) 往OMB2写所要访问的SDRAM地址
(3) 往FIFO写2
3、通过DMA方式从SDRAM读数据的步骤：
(1) 往OMB1写传输数据次数
(2) 往OMB2写所要访问的SDRAM地址
(3) 往FIFO写3
-PCI-driven programming examples, can be implemented through the PCI operation : 2, DMA SDRAM write data to the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to FIFO write 2 3 through DMA side SDRAM-time data from the steps : (a) to transfer data OMB1 write the number (2) to OMB2 was to be visited SDRAM Address (3) to write FIFO 3
Platform: |
Size: 62464 |
Author: 葛琳 |
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Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: |
Size: 19456 |
Author: 朱效志 |
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Description: 该资料为lan91c111芯片的英文原版application note，提供了使用LAN91C111进行开发所需要的软件、硬件设计、功能测试等资料。LAN91C111为SMSC公司生产的以太网控制芯片，为第三代高速以太网连接提供嵌入式解决方案。-The application note of LAN91C111.The SMSC LAN91C111 is a 32/16/8-bit Non-PCI Fast Ethernet controller that integrates on one chip a Media Access Control(MAC)Layer,a Physical Layer(PHY),8k Byte internal Dynamically Configurable TX/RX FIFO SRAM.
Platform: |
Size: 700416 |
Author: Charlie |
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Description: PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
Platform: |
Size: 2048 |
Author: dalchan |
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Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: |
Size: 804864 |
Author: song |
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Description: 3个模块：图像数据采集控制(12C总线)、FIFO读写控制器、与PCI接口芯片通信。- Three modules: image data acquisition and control (12C bus), FIFO read and write controller, and PCI interface chip communication.
Platform: |
Size: 550912 |
Author: 蹇清平 |
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Description: 3个模块：图像数据采集控制(12C总线)、FIFO读写控制器、与PCI接口芯片通信。- Three modules: image data acquisition and control (12C bus), FIFO read and write controller, and PCI interface chip communication.
Platform: |
Size: 550912 |
Author: 蹇清平 |
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Description: 特性
• 符合PCI 2.2版本规范，32位，33MHz总线
• 普通主总线接口，包含两个（可编程的主从数据传输模式和PCI消息功能的）DMA引擎
• 支持PCI v2.2 重要产品数据 (VPD) 配置
• 支持 PCI双地址周期 (DAC)
• PCI Hot Plug and CompactPCI Hot Swap compliant
• I2O™ v1.5-Ready Messaging Unit
• Two independent DMA channels for Local Bus
memory to and from PCI Host Bus Data transfers
• 支持Type 0 和Type 1 配置
• 可编程突发传输管理
• 可编程中断产生器
• 6个可编程并且可0等待突发操作的FIFO
• PCI ↔ Local 数据传输速率达到132 MB/s-pci9054
Platform: |
Size: 180224 |
Author: 何家 |
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Description: PCI 9054性能分析及外部FIFO的扩充-pic bus fifo buffer
Platform: |
Size: 452608 |
Author: hengrj |
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Description: 基于FPGA的PCI ip core 设计源代码，里面包含所有的fifo,状态机源代码，drives 驱动源代码。-“fifo_control.v”
Module FIFO_CONTROL includes control logic for single FIFO. It consists of read and
write address generation and full, almost full, empty and almost empty status generation.
It also generates read and write allow signals, which are used for enabling/disabling
memory used for FIFO. Control logic can be used for independent read and write clocks.
Platform: |
Size: 1946624 |
Author: chen |
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