Search - pci target

[Other resource] 32位-33M 从模式(target)PCI接口参考设计_lattice

Description: 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32 / route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Platform: | Size: 826676 | Author: 陈旭 | Hits:

[Other resource] PCI_144

Description: -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library
Platform: | Size: 2941 | Author: processor | Hits:

[Develop Tools] PCI.Hot-Plug.Specification.v1.0

Description: PCI Hot-Plug Specification Revision 1.0 The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI adapter cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms. -PCI Hot-Plug Specification Revision 1.0 T he primary objective of this specification is not o enable higher availability of file and applic ation servers by standardizing key aspects of t he process of removing and installing PCI adapt er cards while the system is running. Although t hese same principles can be applied to a desktop nd portable systems using PCI buses. the operations described here target server pl atforms.
Platform: | Size: 170385 | Author: asci | Hits:

[Other resource] hgb_pci_host

Description: 内有一PCI 主和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。本PCI_HOST目前支持： 1、对目标PCI_T进行配置； 2、对目标进行单周期读写； 3、可以工作在33MHZ和66MHZ 4、支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的
Platform: | Size: 2713327 | Author: 黄光边 | Hits:

[VHDL-FPGA-Verilog] 32位-33M 从模式(target)PCI接口参考设计_lattice

Description: 32位/33M 从模式(target)PCI接口参考设计，Lattice提供。由于PCI时序较复杂，此设计仅能供参考-32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Platform: | Size: 826368 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] PCI_144

Description: -- PCI Target Interface Design for XC73144 -- -- Synopsys VHDL Solution using Xilinx XC7000 Library --- PCI Target Interface Design for XC73144---- Synopsys VHDL Solution using Xilinx XC7000 Library
Platform: | Size: 3072 | Author: processor | Hits:

[Windows CE] tmman_periph

Description: wince host 和 target PCI驱动程序，支持热插拔。target侧PCI驱动支持philips trimedia处理器-wince host and target PCI driver support Hot Swap. Target side PCI driver support philips trimedia Processor
Platform: | Size: 983040 | Author: 李正路 | Hits:

[Books] PCI.Hot-Plug.Specification.v1.0

Description: PCI Hot-Plug Specification Revision 1.0 The primary objective of this specification is to enable higher availability of file and application servers by standardizing key aspects of the process of removing and installing PCI adapter cards while the system is running. Although these same principles can be applied to desktop and portable systems using PCI buses, the operations described here target server platforms. -PCI Hot-Plug Specification Revision 1.0 T he primary objective of this specification is not o enable higher availability of file and applic ation servers by standardizing key aspects of t he process of removing and installing PCI adapt er cards while the system is running. Although t hese same principles can be applied to a desktop nd portable systems using PCI buses. the operations described here target server pl atforms.
Platform: | Size: 169984 | Author: asci | Hits:

[VHDL-FPGA-Verilog] Pcit32vhdl

Description: PCI 32 target IP for Fpga/asic Designer
Platform: | Size: 428032 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] hgb_pci_host

Description: 内有一PCI 主和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。本PCI_HOST目前支持： 1、对目标PCI_T进行配置； 2、对目标进行单周期读写； 3、可以工作在33MHZ和66MHZ 4、支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
Platform: | Size: 2712576 | Author: | Hits:

[Books] PCI_ZXKZQ

Description: PCI总线目标控制器的设计，一片不错的文章！-PCI bus target controller design, a good article!
Platform: | Size: 149504 | Author: guolh | Hits:

[VHDL-FPGA-Verilog] pci_t

Description: verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
Platform: | Size: 10240 | Author: 齐培红 | Hits:

[Embeded-SCM Develop] plx9054-localbus-cpld-vhdl-src

Description: PLX 公司 PLX9054 pci target controller local bus interface vhdl programe-PLX inc. PLX9054 pci target controller local bus interface vhdl programe
Platform: | Size: 1024 | Author: richardz | Hits:

[Embeded-SCM Develop] DM642pci

Description: DM642 PCI q驱动包括主机端和目标端-DM642 PCI q drive, including the host side and target side
Platform: | Size: 880640 | Author: 刘德坤 | Hits:

[source in ebook] pci_target

Description: pci target design verilog file
Platform: | Size: 53248 | Author: peter | Hits:

[VHDL-FPGA-Verilog] mem32_to_pcitarget_verilog

Description: This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
Platform: | Size: 20480 | Author: minitman | Hits:

[VHDL-FPGA-Verilog] mem64_to_pcitarget_verilog

Description: This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory -This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory
Platform: | Size: 26624 | Author: minitman | Hits:

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