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Description: 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示，简单锁相回路[3,4]是由三个电路构成，分别为相位侦测器（Phase Detector）、回路滤波器（Loop Filter）、压控荡器（VCO）-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input and feedback signals After the output signal. And allowed to operate the same frequency. If (Figure 1), the simple lock-loop [3,4] by the three circuit. for the detection phase (Phase Detector), loop filter (Loop Filter), VCO finishes (VCO)
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Size: 149858 |
Author: 王浩 |
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Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
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Size: 9056 |
Author: mingming |
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Description: 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示，简单锁相回路[3,4]是由三个电路构成，分别为相位侦测器（Phase Detector）、回路滤波器（Loop Filter）、压控荡器（VCO）-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input and feedback signals After the output signal. And allowed to operate the same frequency. If (Figure 1), the simple lock-loop [3,4] by the three circuit. for the detection phase (Phase Detector), loop filter (Loop Filter), VCO finishes (VCO)
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Size: 149504 |
Author: 王浩 |
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Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
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Size: 9216 |
Author: mingming |
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Description: 数字锁相环实现源码，有很大的参考价值。
由 鉴相器 模K加减计数器 脉冲加减电路 同步建立侦察电路 模N分频器 构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and subtraction to establish surveillance mode N divider circuit constituted.
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Size: 2048 |
Author: sharny |
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Description: 使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。-Virlog languages use a phase-locked loop procedure. Can be directly applied in the CPLD.
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Size: 230400 |
Author: 占敖 |
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Description: 2MHz的数据时钟恢复电路，包括鉴相器、分频器及滤波器-2MHz data clock recovery circuit, including phase detector, divider and filter
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Size: 2048 |
Author: Chen |
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Description: 在软件接收机的基础上,利用鉴频器辅助鉴相器的输出,引入一个模糊逻辑控制器,使得环路能够智能跟踪信号的动态变化.实验结果证明所提出的设计方法与传统环路相比可大幅度缩短跟踪时间,减小环路滤波器带宽,并能消除周跳.-In the software receiver, based on the use of auxiliary frequency discriminator phase detector output, the introduction of a fuzzy logic controller, the loop can be intelligent tracking signal dynamics. The experimental results demonstrate that the proposed design method with the traditional loop phase than we might have to significantly reduce the tracking time, reduce the loop filter bandwidth, and can eliminate the cycle slips.
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Size: 344064 |
Author: 何宁 |
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Description: 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
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Size: 53248 |
Author: 颜小山 |
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Description: phase frequency detector verilog
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Size: 13312 |
Author: kdlee |
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Description: PPL讲义，关于鉴相器方面的技术资料，对于用单片机编程有好处。-PPL notes, phase detector on the technical information, good use of single-chip programming.
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Size: 171008 |
Author: 肖伟 |
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Description: 该Si4133是一个单片集成电路，既执行IF和双频
RF合成为无线通信应用。在Si4133
包括三个和VCO，环路滤波器，参考和VCO分频器，相位
探测器。除法和可编程掉电设置与threewire
串行接口。-The Si4133 is a monolithic integrated circuit, both the implementation of the IF and dual-band RF synthesis for wireless communications applications. In the Si4133 consists of three, and VCO, loop filters, reference and VCO divider, phase detector. Division and programmable power-down settings threewire serial interface.
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Size: 470016 |
Author: 峰之巅 |
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Description: Verilog编写基于FPGA的鉴相器模块-Write Verilog FPGA-based phase detector module
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Size: 457728 |
Author: zhh |
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Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。
鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
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Size: 79872 |
Author: Jorge |
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Description: 本文在分析GPS 软件接收机跟踪原理的基础上，首先比较码环与载波环不同鉴相器的性能，然后对二阶锁相环中不同环路参数设下的跟踪效果进行仿真分析，最后设计
了合适的码环与载波环路，并用实际采集的GPS 数据论证了所设计环路的有效性，为GPS 软件接收机跟踪环路的设计提供了参考。-Based on the analysis of GPS receiver tracking software on the basis of the principle, first compare the different code loop and carrier loop phase detector performance, and the different second-order PLL loop parameters set by the tracking simulation analysis, the final design the appropriate code loop and carrier loop, and with real GPS data collected demonstrated the validity of the design loop for GPS receiver tracking loop design software provides a reference.
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Size: 634880 |
Author: herui |
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Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
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Size: 668672 |
Author: 栾帅 |
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Description: 针对锁频锁相器( Phase and Frequency Detector, PFD) 应用于低信噪比、大频偏的条件, 通过理论分析和仿真验证阐述了窗口类型对系统频偏捕获速度、范围、噪声门限及相位噪声抖动的影响机理. 推导出等效相位噪声功率谱密度的表达式. 证明了大窗口具有更低的噪声门限和更小的稳态相位抖动, 但捕获速度较慢. 为了提高捕获速度, 对鉴相器输出值取极性运算得到改进的PFD 算法. 新算法不仅能增加鉴相增益提高捕获速度 还可以减少等效噪声功率谱密度降低相位抖动 同时新算法不需要乘法器便于硬件实现. 最后新算法的性能通过仿真得到了验证.-For frequency-locking phase-locked (Phase and the Frequency Detector PFD) conditions applied to the low signal to noise ratio, frequency offset, through theoretical analysis and simulation described the capture speed of the window type, the system frequency deviation, range, noise threshold and phase noise jitter mechanism. equivalent phase noise power spectral density expression is derived to prove the large windows with a lower noise threshold and the steady-state phase jitter, but to capture slow in order to improve the capture speed, The phase detector output value to take the polarity operator improved PFD algorithm. new algorithm not only can increase the phase gain to improve the capture speed can also reduce the equivalent noise power spectral density to reduce the phase jitter new algorithm does not require a multiplier to facilitate hardware implementation performance of the last new algorithm has been verified through simulation.
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Size: 466944 |
Author: jing |
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Description: 要用phase detector，可到现在还不知道PLL是什么东东，不知道phase detector是如何实现的。 可叹自己没有把事物的因果分析清楚，可叹国外的人懂的比自己多。感谢国外作者的分享。-phase detector PLL demo
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Size: 13312 |
Author: 曾庆勇 |
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Description: Design of a new digital phase detector based on FPGA
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Size: 1526784 |
Author: 595400 |
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Description: This the phase difference calculation method based on digital phase detector DPD.
It uses Hilbert transform to shift one signal the other by 90 degree. Then by some manipulation, extract the phase difference between two signals.-This the phase difference calculation method based on digital phase detector DPD.
It uses Hilbert transform to shift one signal the other by 90 degree. Then by some manipulation, extract the phase difference between two signals.
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Size: 54272 |
Author: fethy16 |
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