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[
VHDL-FPGA-Verilog
]
phase_detector_top_v1.1
Description:
使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。-Virlog languages use a phase-locked loop procedure. Can be directly applied in the CPLD.
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230400
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Author:
占敖
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Search - phase detector FP