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[STL] 1_TO_4

Description: 大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计-large risc processor design source code, which is based on the code book pipelined design of the risc cpu
Platform: | Size: 152576 | Author: | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[source in ebook] CPU_use

Description: 使用VHDL语言编写的简单8位流水线CPU 它有六级流水功能，通过仿真 可以下载到实验箱，也有波形仿真-use VHDL to prepare a simple eight pipelined CPU it has six functional water, Simulation experiments can be downloaded to the box, a waveform simulation
Platform: | Size: 1530880 | Author: 邮件 | Hits:

[Other] VLSIASS2

Description: Self timed pipelined adder
Platform: | Size: 977920 | Author: | Hits:

[VHDL-FPGA-Verilog] cordic_3

Description: 流水线结构的cordic，可以输出sin/cos-Pipelined structure cordic, can output sin/cos
Platform: | Size: 1024 | Author: zq | Hits:

[ARM-PowerPC-ColdFire-MIPS] pis

Description: Computer Architecture pipelined implementation simulator-Computer Architecture pipelinedimplementation simulator
Platform: | Size: 5120 | Author: ludiming | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips3

Description: modelsim+dc开发的4级流水线结构的MIPS CPU，完成基本的逻辑运算和跳转。测试程序为希尔排序，结果正确。-modelsim+ dc development of four pipelined structure MIPS CPU, the completion of the basic logic operations and Jump. Test procedure for the Hill to sort the results correctly.
Platform: | Size: 307200 | Author: 杨春 | Hits:

[VHDL-FPGA-Verilog] mult_piped_8x8

Description: 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
Platform: | Size: 1024 | Author: 江浩 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips_multi

Description: mips processor multicycle non-pipelined microprocessor by verilog
Platform: | Size: 9216 | Author: JACD | Hits:

[Windows Develop] file_encryption

Description: AES分组加密算法做的文件加解密演示, 采用多线程流水线方式对文件进行 读->加密/解密->写 操作.-AES block cipher algorithm for encryption and decryption so the paper presentations, the use of multi-threaded pipelined read on paper-> encryption/decryption-> write operation.
Platform: | Size: 18432 | Author: 周可 | Hits:

[MultiLanguage] Pipelined_Implementation_of_Baseline_JPEG_Encoder

Description: Pipelined Implementation of Baseline JPEG Encoder
Platform: | Size: 974848 | Author: BinhTran | Hits:

[VHDL-FPGA-Verilog] liushuixian_mul

Description: 流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
Platform: | Size: 3072 | Author: snow | Hits:

[VHDL-FPGA-Verilog] cordpipe

Description: pipelined cordic algorithm in hdl
Platform: | Size: 2048 | Author: jai | Hits:

[Other] adc

Description: 1.5-b/s Pipelined A/D behavior model 以及功能包,包括SNR INL DNL测试- 1.5-b/s Pipelined A/D behavior model Include SNR INL DNL test progrems
Platform: | Size: 4096 | Author: jason | Hits:

[Software Engineering] pipeline_6bADC

Description: 6bit pipelined adc in matlab
Platform: | Size: 14336 | Author: Gops | Hits:

[Software Engineering] pipeline_10b_adc

Description: 10bit pipelined adc in matlab
Platform: | Size: 20480 | Author: Gops | Hits:

[Other] FFT

Description: 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
Platform: | Size: 149504 | Author: liu | Hits:

[matlab] 4-10-bit-Pipelined-ADC-Model

Description: model non linear of 10 bit Pipelined ADC
Platform: | Size: 34816 | Author: spartansamir | Hits:

[matlab] Pipelined-ADC

Description: pipelined ADC, 各种参数可调，最后包括fft分析和整个传输曲线-pipelined ADC, adjustable parameters, and finally including the entire transfer curve analysis and fft
Platform: | Size: 18432 | Author: 郑宇龙 | Hits:

[matlab] SNDR-test-for-pipelined-ADC

Description: 流水线ADC信噪比测试程序,最后一级flash位数可调，可进行SNDR和SFDR的测试-SNDR test for pipelined ADC
Platform: | Size: 3072 | Author: colin | Hits:
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