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Description: A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
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Size: 236523 |
Author: 谢振 |
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Description:
Fast settling-time added to the already conflicting requirements of narrow channel spacing and
low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete \"beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
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Size: 418324 |
Author: 谢振 |
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Description: This paper presents various applications of a nonlinear
adaptive notch filter which operates based on the concept
of an enhanced phase-locked loop (PLL). Applications of the filter
for online signal analysis for power systems protection, control and
power quality enhancement are presented. The proposed scheme
can be applied for signal analysis both under stationary and nonstationary
conditions. Based on digital time-domain simulations,
applications of the filter for a) sinusoidal waveform peak detection,
b) harmonic identification/detection, c) detection/extraction
of individual components of a signal, d) instantaneous reactive
current extraction, e) disturbance detection, f) noise reduction in
zero-crossings detection, and g) amplitude (phase) demodulation
for flicker estimation, are presented.
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Size: 153503 |
Author: yangyansky |
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Description: A new PLL topology and a new simplified linear model are presented. The new fractional-N synthesizer presents no reference spurs and lowers the overall phase noise, thanks to the presence of a SampleJHold block. With a new simulation methodology it is possible to perform very accurate simulations, whose results match closely those obtained with the linear PLL model developed.
Platform: |
Size: 236544 |
Author: 谢振 |
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Description:
Fast settling-time added to the already conflicting requirements of narrow channel spacing and
low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
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Size: 417792 |
Author: 谢振 |
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Description: 对于如何设计数字PLL的参数很有帮助.
分析了在最小等效噪声带宽，最小相位均方误差，以及最短锁定时间三种意义上的参数优化设计-For how to design the parameters of the digital PLL helpful. Analysis of the minimum noise equivalent bandwidth, minimum-phase mean-square error, as well as the minimum lockout time of three within the meaning of parameter optimization design
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Size: 82944 |
Author: 葭葭 |
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Description: 介绍了一种基于锁频锁相环(FPLL)的载波跟踪算法。频率跟踪模块可以适应较大动态范围的频率变化，基于软件的数控振荡器(NCO)模块可以达到极高的频率跟踪精度。由于有锁频环的频率牵引，锁相环路滤波器可以设计得很窄，具有很好的抑噪性能，满足精确跟踪载波相位的要求。因此，该基于FPLL的载波跟踪算法可以适应信号存在较大的动态范围和噪声干扰的应用环境；同时，其鉴频鉴相算法表达式简单，易于用可编程数字器件实现。-Introduce an approach based on frequency-locking phase-locked loop (FPLL) carrier tracking algorithm. Frequency tracking module can adapt to a larger dynamic range of the frequency change, software-based numerical control oscillator (NCO) module can achieve the very high frequency tracking accuracy. Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking. Therefore, the FPLL carrier-based tracking algorithm can be adapted to signal the existence of a larger dynamic range and noise of the application environment at the same time, the PFD algorithm expression is simple, easy to use programmable digital devices.
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Size: 162816 |
Author: 何宁 |
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Description: 小数分频技术解决了锁相环频率合成器中的频率分辨率和转换时间的矛盾, 但是却引入了严重的相位噪声,
传统的相位补偿方法由于对Aö D 等数字器件的要求很高并具有滞后性实现难度较大。$2 调制器对噪声具有整形的功
能, 因而将多阶的$2 调制器用于小数分频合成器中可以很好地解决他的相位噪声的问题, 大大促进了小数分频技术的
发展和应用。文章最后给出了在GHz 量级上实现的这种新型小数分频合成器的应用电路, 并测得良好的相噪性能。-Fractional-N technology to solve the PLL frequency synthesizer in the frequency resolution and conversion time of contradictions, but the introduction of a serious phase noise, the traditional method of phase compensation A? D because of the number of devices, such as demanding and have the lag is more difficult to achieve. $ 2 modulator with noise shaping function, and thus will be more than the $ 2-order modulator for fractional-N synthesizer can be a good solution to his problem of phase noise, contributed significantly to the fractional-N technology development and applications. Finally, the article in the GHz order to achieve this new fractional-N synthesizer of the application circuit, and measured a good phase noise performance.
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Size: 286720 |
Author: 朱成发 |
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Description: 瞬时频率的解释和瞬时频率估计算法的介绍，回顾目前存在的一些瞬时频率估计算法以及作者提出的新的算法-This paper, which addresses the important issue of estimating
the instantaneous frequency (IF) of a signal, is a sequel to the
paper which appears in this issue, and dealt with the concepts
relating to the IF. In this paper the concept of IF is extended to
be able to cope with discrete time signals. The specific problem explored is that of estimating the IF of frequency modulated
(FM) discrete-time signals imbedded in Gaussian noise. There are many well established methods for estimating the IF-these methods include differentiation of the phase and smoothing thereof adaptive frequency estimation techniques such as the phase locked loop (PLL), and extraction of the peak from time-varying spectral
representations. More recently methods based on a modeling of the signal phase as a polynomial have been introduced. All of these methods are reviewed, and their performances are compared on both simulated and real data. Guidelines are
given as to which estimationmethodshould be used for
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Size: 2171904 |
Author: sunrong |
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Description: matlab对PLL环路相位噪声的仿真m文件-simulation of PLL loop phase noise
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Size: 1024 |
Author: chenmy |
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Description: PLL相位噪声仿真方法总结,用来说明对各个模块相位噪声仿真的方法-PLL phase noise simulation document
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Size: 52224 |
Author: chenmy |
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Description: pll phasenregler
The ltering operation of the error voltage (coming out from the Phase Detec-
tor) is performed by the loop lter. The output of PD consists of a dc component
superimposed with an ac component. The ac part is undesired as an input to the
VCO, hence a low pass lter is used to lter out the ac component. Loop lter is
one of the most important functional block in determining the performance of the
loop. A loop lter introduces poles to the PLL transfer function, which in turn is a
parameter in determining the bandwidth of the PLL. Since higher order loop lters
o er better noise cancelation, a loop lter of order 2 or more are used in most of the
critical application PLL circuits.
8
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Size: 348160 |
Author: mtms |
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Description: The ltering operation of the error voltage (coming out from the Phase Detec-
tor) is performed by the loop lter. The output of PD consists of a dc component
superimposed with an ac component. The ac part is undesired as an input to the
VCO, hence a low pass lter is used to lter out the ac component. Loop lter is
one of the most important functional block in determining the performance of the
loop. A loop lter introduces poles to the PLL transfer function, which in turn is a
parameter in determining the bandwidth of the PLL. Since higher order loop lters
o er better noise cancelation, a loop lter of order 2 or more are used in most of the
critical application PLL circuits.
8
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Size: 33792 |
Author: mtms |
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Description: Digital GNSS PLL Design
Conditioned on Thermal and
Oscillator Phase Noise
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Size: 1757184 |
Author: 小庄 |
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Description: In a series of papers in recent years new
structures for coherent M-PSK (M-ary Phase Shift Keying)
receivers were suggested. These include structures for carrier
phase detectors for the carrier PLL (Phase Lock Loop),
carrier PLL lock detectors, symbol timing error detectors,
symbol synchronization PLL lock detectors, carrier and
symbol PLL loop filters, and SNR (Signal to Noise Ratio)
estimators
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Size: 451584 |
Author: lala |
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Description: Hittite公司以创新的设计使得其PLL产品性能优异，在相位噪声，杂散方面有着卓越表现，其芯片的高集成度使得外围电路简单，设计方便。所以随着电子技术的发展，对频率源的相位噪声性能要求越来越高，Hittite的低相位噪声PLL，在物理、天文、无线电通信、雷达、航空、航天以及精密计量、仪器、仪表等各种领域里都将大有用武之地。-The Hittite companies with innovative design makes the PLL excellent product performance, the phase noise, spurious aspects with excellence, its high integration chip makes the peripheral circuit is simple and easy design. So with the development of electronic technology, phase noise performance of frequency source is more and more high, the Hittite low phase noise PLL, in physics, astronomy, radio communication, radar, aviation, aerospace and precision measurement, instruments, meters and other fields will be great.
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Size: 4281344 |
Author: 915809706 |
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Description: 快速锁定，集成VCO，小数分频PLL，宽频带，细不进，超低相位噪声及杂散、谐波抑制性高-Fast lock-in, integrated VCO, fractional-PLL, wideband, fine-in, ultra-low phase noise and spurious, high harmonic rejection
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Size: 1073152 |
Author: 吴彬 |
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Description: PLL 相噪分析matlab代码，可以用以分析整个系统相噪。(PLL phase noise analysis matlab code)
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Size: 1024 |
Author: 水静天悟
|
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Description: ADF4355是微波宽带(54-6800MHz)可实现小数N分频或整数N分频锁相环(PLL)的频率合成器,高分辨率38位模数,低相位噪声电压控制振荡器(VCO),可编程1/2/4/8/16/32/64分频输出,模拟和数字电源为3.3 V,主要用在无线基础设施（W-CDMA,TD-SCDMA,WiMAX,GSM, PCS,DCS,DECT）,点到点/点到多点微波链路(ADF4355 microwave broadband (54-6800 MHZ) can realize the decimal frequency or integer N N points points frequency and phase lock loop (PLL) frequency synthesizer, 38 modulus, high resolution and low phase noise voltage controlled oscillator (VCO), programmable 1/2/4 8/16/32/64 frequency output, analog and digital power supply of 3.3 V, mainly used in wireless infrastructure (w-cdma, td-scdma, WiMAX, GSM, PCS, DCS, DECT), point-to-point/point to multipoint microwave links)
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Size: 764928 |
Author: 悟与 |
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Description: 计算PLL环路的传递函数，环路带宽，相位裕度等参数；
根据相位噪声大致估算对应的输出信号的jitter(calculate the transformer function, bandwidth, phase margin .etc;
and calculate the jitter from phase noise;)
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Size: 1024 |
Author: 陌月 |
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