Description: 二阶锁相环Matlab仿真代码，如入两路信号和信噪比，输出锁相以后的信号。可以仿真初始频差，和频率斜升的情况-second-order PLL Matlab simulation code, such as two-way signals and signal to noise ratio, the output signal after the lock-in. Simulation can initial frequency difference, and frequency ramp-up of Platform: |
Size: 2048 |
Author:里根 |
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Description: 关于锁相环（PLL）的经典教程，有相关matlab仿真程序的详细说明。来自国外的十分珍贵的资料。-With regard to phase-locked loop (PLL) of the classic tutorial matlab simulation program with relevant details. From abroad is very valuable information. Platform: |
Size: 65536 |
Author:yxyAlbert |
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Description: 用ADS和matlab进行了PLL的仿真实现，对与PLL的学习有一定的作用-Carried out with the ADS and the PLL matlab simulation realization, and the PLL has a role in learning Platform: |
Size: 367616 |
Author:建伟 |
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Description: 用matlab模拟仿真锁相环，一个很好的程序，希望能帮到你-PLL with matlab simulation, a very good program, hope you can help Platform: |
Size: 1024 |
Author:偶轩昂亲 |
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Description: 该压缩文件是一个用matlab实现数字锁相环仿真的程序-The compressed file is a digital PLL with matlab simulation program Platform: |
Size: 2048 |
Author:marlin |
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Description: 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全
数字锁相环的仿真模型 对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable to all-digital phase-locked loop DPLL layout SPICE simulation, with the The model simulation results verified. Platform: |
Size: 259072 |
Author:dashu |
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Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.) Platform: |
Size: 10222592 |
Author:丶大娱乐家 |
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