Search - pll simulink model

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[Other resource] DPLL1lp DL : 0: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Update : 2008-10-13 Size : 8.24kb Publisher : rossi
[Other] grew DL : 0: 为了测量 DVD的Jitter ,需要知道刻录时钟。针对 DVD 特殊的数据格式 NRZI,提出一个专用的时钟恢复系统 ,用于从读出的 RF信号中恢复写时钟。这个系统采用基于锁相环的双环结构。介绍系统结构、各个模块的构成原理、数学模型 ,并结合 Simulink 给出仿真结果。理论和实验证明 ,该系统既可作为测量 DVD Jitter 的硬件电路设计的参考 ,也可作为软件设计的工具。-DVD to the Jitter measurement, the burning need to know the clock. DVD special against the NRZI data format, a dedicated clock to restore the system, From time for the RF signal was restored clock. The system based on the dual-loop PLL structure. On the structure, the various modules of the composition theory, mathematical model, and is integrated Simulink simulation results. Theory and experiment proved that the system can measure DVD Jitter as the hardware circuit design reference can also be used as the design of software tools.
Update : 2008-10-13 Size : 396.44kb Publisher : 熊静
[matlab] DPLL1lp DL : 0: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Update : 2025-02-19 Size : 8kb Publisher : rossi
[Other] grew DL : 0: 为了测量 DVD的Jitter ,需要知道刻录时钟。针对 DVD 特殊的数据格式 NRZI,提出一个专用的时钟恢复系统 ,用于从读出的 RF信号中恢复写时钟。这个系统采用基于锁相环的双环结构。介绍系统结构、各个模块的构成原理、数学模型 ,并结合 Simulink 给出仿真结果。理论和实验证明 ,该系统既可作为测量 DVD Jitter 的硬件电路设计的参考 ,也可作为软件设计的工具。-DVD to the Jitter measurement, the burning need to know the clock. DVD special against the NRZI data format, a dedicated clock to restore the system, From time for the RF signal was restored clock. The system based on the dual-loop PLL structure. On the structure, the various modules of the composition theory, mathematical model, and is integrated Simulink simulation results. Theory and experiment proved that the system can measure DVD Jitter as the hardware circuit design reference can also be used as the design of software tools.
Update : 2025-02-19 Size : 396kb Publisher : 熊静
[VHDL-FPGA-Verilog] pll DL : 0: 模拟锁相环（apll）的一些simulink模型-Analog phase-locked loop (apll) some simulink model
Update : 2025-02-19 Size : 717kb Publisher : prescaler
[matlab] PhaseLockedLoop DL : 0: This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL). The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors. -This tutorial starts with a simple conceptual model of an analog Phase-Locked Loop (PLL). Through elaboration it ends at a model of an all digital and fixed-point phase-locked loop. The final model can serve a starting point for code generation (both ANSI C or synthesizable HDL). The step-wise elaboration of the model illustrates how Simulink® forms the basis a model-based design where continuous verification of the model reduces errors.
Update : 2025-02-19 Size : 390kb Publisher : 张骅
[source in ebook] QPSK_awgn DL : 0: 一个QPSK的simulink模型，希望对大家有用，-The simulink model of a PLL, we want to be useful, thank you
Update : 2025-02-19 Size : 7kb Publisher : 李响
[matlab] pll DL : 0: pll simulink model. noise and system model
Update : 2025-02-19 Size : 1.43mb Publisher : khosro raja
[matlab] PLL DL : 0: matlab-simulink的锁相环模型-pll model
Update : 2025-02-19 Size : 7kb Publisher : 叶明
[matlab] eetop.cn_pll_integer_N DL : 0: 整数锁相环的malab 建模与仿真程序用于行为及的验证与仿真对PLL建模有好处-simulink of integer PLL simulation model and testbench
Update : 2025-02-19 Size : 9kb Publisher : dante
[OS program] pll_behavior_3th_cp DL : 0: 一個簡單的PLL(Phase Locked Loop)鎖相迴路的 Simulink行為模型-Simulink behavior model a simple PLL (Phase Locked Loop) phase-locked loop
Update : 2025-02-19 Size : 78kb Publisher : alia
[Other] SinglePhaseLockLoop DL : 0: single phase voltage PLL,simulink simulation model
Update : 2025-02-19 Size : 8kb Publisher : bruce chen
[Other] findEulerAngs DL : 0: 接收机同步PLL模型文件，可以采用matlab/simulink软件编辑操作，适合软件无线电的初学者以及其他相关行业。-Receiver synchronization PLL model file, you can use matlab/simulink software editing operation, suitable for beginners and other related software radio industry.
Update : 2025-02-19 Size : 14kb Publisher : dlbuaa
[matlab] LAB8_13 DL : 0: 利用MATLAB Simulink內建Model，模擬一階鎖相迴路系統(Analog first-order PLL system)
Update : 2025-02-19 Size : 7kb Publisher : chou950
[matlab] PLL_simulink DL : 0: pll锁相环simulink模型，通俗易懂，可以实现的模型(Pll phase locked loop simulink model, easy to understand, can achieve the model)
Update : 2025-02-19 Size : 459kb Publisher : 182505196527
[Other] 系统仿真程序代码 DL : 0: 通信系统建模与仿真实例分析 simulink 原码(Matlab/simulink PLL/ADC model)
Update : 2025-02-19 Size : 749kb Publisher : 特